Issued Patents All Time
Showing 26–50 of 60 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7728623 | Programmable logic cells with local connections | Hare K. Verma, Sudip K. Nag, Conrad Kong, Bo Hu, Chandra Mulpuri +1 more | 2010-06-01 |
| 7605605 | Programmable logic cells with local connections | Hare K. Verma, Sudip K. Nag, Conrad Kong, Bo Hu, Chandra Mulpuri +1 more | 2009-10-20 |
| 7439768 | Dedicated logic cells employing configurable logic and dedicated logic functions | Hare K. Verma, Manoj Gunwani, Elliott Delaye | 2008-10-21 |
| 7428722 | Versatile multiplexer-structures in programmable logic using serial chaining and novel selection schemes | Hare K. Verma, Sudip K. Nag, Elliott Delaye | 2008-09-23 |
| 7417456 | Dedicated logic cells employing sequential logic and control logic functions | Hare K. Verma, Manoj Gunwani, Chandra Mulpuri | 2008-08-26 |
| 7414431 | Dedicated logic cells employing configurable logic and dedicated logic functions | Hare K. Verma, Manoj Gunwani, Elliott Delaye | 2008-08-19 |
| 7414432 | Dedicated logic cells employing sequential logic and control logic functions | Hare K. Verma, Manoj Gunwani, Chandra Mulpuri | 2008-08-19 |
| 7368941 | Dedicated logic cells employing sequential logic and control logic functions | Hare K. Verma, Manoj Gunwani, Chandra Mulpuri | 2008-05-06 |
| 7358765 | Dedicated logic cells employing configurable logic and dedicated logic functions | Hare K. Verma, Manoj Gunwani, Elliott Delaye | 2008-04-15 |
| 7358761 | Versatile multiplexer-structures in programmable logic using serial chaining and novel selection schemes | Hare K. Verma, Sudip K. Nag, Elliott Delaye | 2008-04-15 |
| 7176717 | Programmable logic and routing blocks with dedicated lines | Hare K. Verma, Chandra Mulpuri, Elliott Delaye | 2007-02-13 |
| 6555436 | Simultaneous formation of charge storage and bitline to wordline isolation | Mark T. Ramsbey, Jean Y. Yang, Hidehiko Shiraiwa, Michael A. Van Buskirk, David Michael Rogers +3 more | 2003-04-29 |
| 6541816 | Planar structure for non-volatile memory devices | Mark T. Ramsbey, Jean Y. Yang, Hidehiko Shiraiwa, Michael A. Van Buskirk, David Michael Rogers +2 more | 2003-04-01 |
| 6493261 | Single bit array edges | Darlene Hamilton, Kulachet Tanpairoj, Narbeh Derhacobian, Michael A. Van Buskirk | 2002-12-10 |
| 6490205 | Method of erasing a non-volatile memory cell using a substrate bias | Janet Wang | 2002-12-03 |
| 6468865 | Method of simultaneous formation of bitline isolation and periphery oxide | Jean Y. Yang, Mark T. Ramsbey, Hidehiko Shiraiwa, Michael A. Van Buskirk, David Michael Rogers +3 more | 2002-10-22 |
| 6465306 | Simultaneous formation of charge storage and bitline to wordline isolation | Mark T. Ramsbey, Jean Y. Yang, Hidehiko Shiraiwa, Michael A. Van Buskirk, David Michael Rogers +3 more | 2002-10-15 |
| 6465303 | Method of manufacturing spacer etch mask for silicon-oxide-nitride-oxide-silicon (SONOS) type nonvolatile memory | Mark T. Ramsbey, Narbeh Derhacobian, Janet Wang, Angela T. Hui, Tuan Pham +1 more | 2002-10-15 |
| 6452840 | Feedback method to optimize electric field during channel erase of flash memory devices | Lee Cleveland, Sameer Haddad, Richard Fastow, Tim Thurgate | 2002-09-17 |
| 6442074 | Tailored erase method using higher program VT and higher negative gate erase | Darlene Hamilton, Kulachet Tanpairoj, Narbeh Derhacobian | 2002-08-27 |
| 6385093 | I/O partitioning system and methodology to reduce band-to-band tunneling current during erase | Edward V. Bautista, Jr., Kazuhiro Kurihara, Feng Pan, Weng Fook Lee, Darlene Hamilton | 2002-05-07 |
| 6331952 | Positive gate erasure for non-volatile memory cells | Janet Wang, Narbeh Derhacobian | 2001-12-18 |
| 6307784 | Negative gate erase | Darlene Hamilton, Narbeh Derhacobian, Kulachet Tanpairoj | 2001-10-23 |
| 6275415 | Multiple byte channel hot electron programming using ramped gate and source bias voltage | Sameer Haddad, Wing Leung, John Chen, Ravi Prakash Gutala, Colin S. Bill +1 more | 2001-08-14 |
| 6243300 | Substrate hole injection for neutralizing spillover charge generated during programming of a non-volatile memory cell | — | 2001-06-05 |