| 11651127 |
Placement of logic based on relative activation rates |
Jianyi Cheng |
2023-05-16 |
| 11422781 |
Generation of vector codes for tensor convolutions |
Prasanth Chatarasi, Samuel R. Bayliss |
2022-08-23 |
| 10671779 |
Function calls in high level synthesis |
— |
2020-06-02 |
| 10031732 |
Operation processing for high level synthesis |
Dong Li, Sheng Zhou |
2018-07-24 |
| 9824172 |
Performance of circuitry generated using high-level synthesis |
Kecheng Hao, Hongbin Zheng |
2017-11-21 |
| 9710584 |
Performance of circuitry generated using high-level synthesis |
Kecheng Hao, Hongbin Zheng |
2017-07-18 |
| 9449131 |
Extracting system architecture in high level synthesis |
Guoling Han |
2016-09-20 |
| 9081930 |
Throughput during high level synthesis |
Kecheng Hao, Guoling Han |
2015-07-14 |
| 8359448 |
Specific memory controller implemented using reconfiguration |
— |
2013-01-22 |
| 8245243 |
Transforming device drivers to improve efficiency |
— |
2012-08-14 |
| 8219960 |
Methods of implementing relocatable circuits in a programmable integrated circuit device |
Parimal Patel |
2012-07-10 |
| 8122239 |
Method and apparatus for initializing a system configured in a programmable logic device |
Philip B. James-Roxby, Henry E. Styles |
2012-02-21 |
| 8116334 |
Dataflow FIFO communication buffer using highly-multiported memories |
— |
2012-02-14 |
| 8020139 |
Method and apparatus for implementing a dataflow circuit model using application-specific memory implementations |
Ian Miller |
2011-09-13 |
| 7969187 |
Hardware interface in an integrated circuit |
Paul M. Hartke, Paul R. Schumacher |
2011-06-28 |
| 7895026 |
Multi-rate simulation scheduler for synchronous digital circuits in a high level modeling system |
Sean A. Kelly, Haibing Ma |
2011-02-22 |
| 7869452 |
Dataflow FIFO communication buffer using highly-multiported memories |
— |
2011-01-11 |
| 7834658 |
Interface generation for coupling to a high-bandwidth interface |
Paul M. Hartke, Paul R. Schumacher |
2010-11-16 |
| 7765512 |
Relocatable circuit implemented in a programmable logic device |
Parimal Patel |
2010-07-27 |
| 7653762 |
Profiling circuit arrangement |
Peter Oruba |
2010-01-26 |
| 7541833 |
Validating partial reconfiguration of an integrated circuit |
Brandon J. Blodget |
2009-06-02 |
| 7525343 |
Method and apparatus for accessing internal registers of hardware blocks in a programmable logic device |
Brandon J. Blodget |
2009-04-28 |