Issued Patents All Time
Showing 26–50 of 56 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7243330 | Method and apparatus for providing self-implementing hardware-software libraries | Satish R. Ganesan, Amit Kasat, Sathyanarayanan Thammanur, Sundararajarao Mohan, Usha Prabhu | 2007-07-10 |
| 7181718 | Structures and methods providing columns of tightly coupled processor and RAM blocks within an array of logic blocks | Goran Bilski, Jennifer Wong, David B. Squires | 2007-02-20 |
| 7145360 | Configurable logic element with expander structures | Bernard J. New, Sundararajarao Mohan | 2006-12-05 |
| 7111273 | Softpal implementation and mapping technology for FPGAs with dedicated resources | Satish R. Ganesan, Sundararajarao Mohan | 2006-09-19 |
| 6946874 | Structures and methods providing columns of tightly coupled processor and RAM blocks within an array of logic blocks | Goran Bilski, Jennifer Wong, David B. Squires | 2005-09-20 |
| 6847229 | Configurable logic element with expander structures | Bernard J. New, Sundararajarao Mohan | 2005-01-25 |
| 6803786 | Structures and methods providing columns of tightly coupled processor and RAM blocks within an array of logic blocks | Goran Bilski, Jennifer Wong, David B. Squires | 2004-10-12 |
| 6630841 | Configurable logic element with expander structures | Bernard J. New, Sundararajarao Mohan | 2003-10-07 |
| 6603332 | Configurable logic block for PLD with logic gate for combining output with another configurable logic block | Alireza S. Kaviani, Sundararajarao Mohan, Steven P. Young, Bernard J. New | 2003-08-05 |
| 6583645 | Field programmable optical arrays | David W. Bennett, Sundararajarao Mohan | 2003-06-24 |
| 6505337 | Method for implementing large multiplexers with FPGA lookup tables | Sundararajarao Mohan | 2003-01-07 |
| 6501296 | Logic/memory circuit having a plurality of operating modes | Sundararajarao Mohan, Richard A. Carberry | 2002-12-31 |
| 6457164 | Hetergeneous method for determining module placement in FPGAs | L. James Hwang, Eric F. Dellinger, Sujoy Mitra, Sundararajarao Mohan, Cameron Patterson | 2002-09-24 |
| 6400180 | Configurable lookup table for programmable logic devices | Sundararajarao Mohan, Bernard J. New | 2002-06-04 |
| 6396302 | Configurable logic element with expander structures | Bernard J. New, Sundararajarao Mohan | 2002-05-28 |
| 6388466 | FPGA logic element with variable-length shift register capability | Sundararajarao Mohan, Bernard J. New | 2002-05-14 |
| 6353920 | Method for implementing wide gates and tristate buffers using FPGA carry logic | Sundararajarao Mohan, Hamish T. Fallside | 2002-03-05 |
| 6292925 | Context-sensitive self implementing modules | Eric F. Dellinger, L. James Hwang, Sujoy Mitra, Sundararajarao Mohan | 2001-09-18 |
| 6288569 | Memory array with hard and soft decoders | Sundararajarao Mohan, Richard A. Carberry | 2001-09-11 |
| 6259205 | High-pressure discharge lamp with a discharge vessel having conical of concentric ends | Christoffel Wijenberg, Bernardus Lambertus Martinus Van Bakel, Sundararajarao Mohan | 2001-07-10 |
| 6260182 | Method for specifying routing in a logic module by direct module communication | Sundararajarao Mohan, Eric F. Dellinger, L. James Hwang, Sujoy Mitra | 2001-07-10 |
| 6243851 | Heterogeneous method for determining module placement in FPGAs | L. James Hwang, Eric F. Dellinger, Sujoy Mitra, Sundararajarao Mohan, Cameron Patterson | 2001-06-05 |
| 6237129 | Method for constraining circuit element positions in structured layouts | Cameron Patterson, Eric F. Dellinger, L. James Hwang, Sujoy Mitra, Sundararajarao Mohan | 2001-05-22 |
| 6216258 | FPGA modules parameterized by expressions | Sundararajarao Mohan, Eric F. Dellinger, L. James Hwang, Sujoy Mitra | 2001-04-10 |
| 6208163 | FPGA configurable logic block with multi-purpose logic/memory circuit | Sundararajarao Mohan, Richard A. Carberry | 2001-03-27 |