Issued Patents All Time
Showing 1–25 of 25 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8332796 | FPGA with hybrid interconnect | — | 2012-12-11 |
| RE41548 | FPGA with hybrid interconnect | — | 2010-08-17 |
| 7703065 | FPGA with hybrid interconnect | — | 2010-04-20 |
| 7679398 | Reprogrammable instruction DSP | — | 2010-03-16 |
| 7241635 | Binning for semi-custom ASICs | — | 2007-07-10 |
| 7093225 | FPGA with hybrid interconnect | — | 2006-08-15 |
| 7062744 | Emulation solution for programmable instruction DSP | — | 2006-06-13 |
| 7055125 | Depopulated programmable logic array | Patrick Hallinan, Jung Seop Lee, Shridhar Mukund | 2006-05-30 |
| 7043713 | Implementing programmable logic array embedded in mask-programmed ASIC | Shafy Eltoukhy, Shridhar Mukund, Lyle Smith | 2006-05-09 |
| 6804812 | Depopulated programmable logic array | Patrick Hallinan, Jung Seop Lee, Shridhar Mukund | 2004-10-12 |
| 6769109 | Programmable logic array embedded in mask-programmed ASIC | Shafy Eltoukhy, Shridhar Mukund, Lyle Smith | 2004-07-27 |
| 6694491 | Programmable logic array embedded in mask-programmed ASIC | Shafy Eltoukhy, Shridhar Mukund, Lyle Smith | 2004-02-17 |
| 6613611 | ASIC routing architecture with variable number of custom masks | Dana How, Eric F. Dellinger | 2003-09-02 |
| 6611932 | Method and apparatus for controlling and observing data in a logic block-based ASIC | Dana How, Adi Srinivasan, Shridhar Mukund | 2003-08-26 |
| 6498361 | Design information memory for configurable integrated circuits | — | 2002-12-24 |
| 6399400 | Methods and apparatuses for binning partially completed integrated circuits based upon test results | Shafy Eltoukhy | 2002-06-04 |
| 6223313 | Method and apparatus for controlling and observing data in a logic block-based asic | Dana How, Adi Srinivasan, Shridhar Mukund | 2001-04-24 |
| 6150807 | Integrated circuit architecture having an array of test cells providing full controllability for automatic circuit verification | — | 2000-11-21 |
| 6133582 | Methods and apparatuses for binning partially completed integrated circuits based upon test results | Shafy Eltoukhy | 2000-10-17 |
| 5872448 | Integrated circuit architecture having an array of test cells providing full controlability for automatic circuit verification | — | 1999-02-16 |
| 5640308 | Field programmable circuit module | George Shaw, Amr M. Mohsen | 1997-06-17 |
| 5506850 | Logic analyzer for high channel count applications | — | 1996-04-09 |
| 5414638 | Programmable interconnect architecture | Henry Verheyen, Charles KRING | 1995-05-09 |
| 5383787 | Integrated circuit package with direct access to internal signals | Andrew Switky | 1995-01-24 |
| 5384433 | Printed circuit structure including power, decoupling and signal termination | Jeffery A. Ausman, David R. Halbert | 1995-01-24 |