AS

Adi Srinivasan

AP Aptix: 9 patents #2 of 21Top 10%
SD Sequence Design: 7 patents #2 of 23Top 9%
LS Lightspeed Semiconductor: 6 patents #4 of 14Top 30%
GA Gradient Design Automation: 4 patents #2 of 10Top 20%
Overall (All Time): #155,892 of 4,157,543Top 4%
26
Patents All Time

Issued Patents All Time

Showing 25 most recent of 26 patents

Patent #TitleCo-InventorsDate
8286111 Thermal simulation using adaptive 3D and hierarchical grid mechanisms Rajit Chandra, John Yanjiang Shu, Paolo Carnevali 2012-10-09
8019580 Transient thermal analysis Rajit Chandra, Paolo Carnevali, John Yanjiang Shu 2011-09-13
7823102 Thermally aware design modification Rajit Chandra, Nanda Gopal 2010-10-26
7353471 Method and apparatus for using full-chip thermal analysis of semiconductor chip designs to compute thermal conductance Rajit Chandra 2008-04-01
7222318 Circuit optimization for minimum path timing violations — 2007-05-22
7003741 Method for determining load capacitance — 2006-02-21
6954917 Function block architecture for gate array and method for forming an asic Dana How, Abbas El Gamal 2005-10-11
6754877 Method for optimal driver selection — 2004-06-22
6701505 Circuit optimization for minimum path timing violations — 2004-03-02
6701506 Method for match delay buffer insertion David L. Allen 2004-03-02
6701507 Method for determining a zero-skew buffer insertion point — 2004-03-02
6698006 Method for balanced-delay clock tree insertion David L. Allen 2004-02-24
6690194 Function block architecture for gate array Dana How, Abbas El Gamal 2004-02-10
6611932 Method and apparatus for controlling and observing data in a logic block-based ASIC Dana How, Robert Osann, Jr., Shridhar Mukund 2003-08-26
6242767 Asic routing architecture Dana How, Abbas El Gamal 2001-06-05
6223313 Method and apparatus for controlling and observing data in a logic block-based asic Dana How, Robert Osann, Jr., Shridhar Mukund 2001-04-24
6014038 Function block architecture for gate array Dana How, Abbas El Gamal 2000-01-11
5406138 Programmable interconnect architecture using fewer storage cells than switches Ta-Pen Guo 1995-04-11
5400294 Memory cell with user-selectable logic state on power-up Ta-Pen Guo 1995-03-21
5367482 High voltage random-access memory cell incorporation level shifter Ta-Pen Guo 1994-11-22
5319261 Reprogrammable interconnect architecture using fewer storage cells than switches Hong Cai, Ta-Pen Guo 1994-06-07
5315545 High-voltage five-transistor static random access memory cell Ta-Pan Guo 1994-05-24
5301147 Static random access memory cell with single logic-high voltage level bit-line and address-line drivers Ta-Pen Guo 1994-04-05
5264741 Low current, fast, CMOS static pullup circuit for static random-access memories Ta-Pen Guo 1993-11-23
5257239 Memory cell with known state on power-up Ta-Pen Guo 1993-10-26