Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Test methodology for direct interconnect with multiple fan-outs

Test methodology for direct interconnect with multiple fan-outs

US Patent 6943581 · Granted Sep 13, 2005

Estimated economic value: $11,909,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Flexible manufacturing flow enabled by adaptive binning system2020
Internal voltage level shifting for screening cold or hot temperature defects us2011
Method and apparatus for testing a memory device with a redundant self repair fe2009
Testing of input/output devices of an integrated circuit2009
Method and apparatus for eliminating noise induced errors during test of a progr2009
Method for gross I/O functional test at wafer sort2007
Methods of testing interconnect lines in programmable logic devices using partia2006
Methods of resource optimization in programmable logic devices to reduce test ti2005
Method and apparatus for localizing faults within a programmable logic device2005
Method for gross input leakage functional test at wafer sort2004