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USPTO Patent Rankings Data through Dec 31, 2025
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Wilson K. Yee — 13 Patents

AMD: 10 patents #1,333 of 9,280Top 15%
BSBrocade Communications Systems: 1 patents #286 of 504Top 60%
TRTriscend: 1 patents #11 of 17Top 65%
Tracy, CA: #43 of 508 inventorsTop 9%
California: #47,433 of 386,348 inventorsTop 15%
Overall (All Time): #362,438 of 4,157,543Top 9%
13 Patents All Time
Wilson K. Yee has been granted 13 US patents while listed as an inventor at AMD. The first was granted in 1995 and the most recent in August 2010. Wilson K. Yee ranks #362,438 of 4,157,543 US inventors in our database (top 8.7%). Patent records list Wilson K. Yee in Tracy, CA, US.

Issued Patents All Time

Showing 1–13 of 13 patents

Patent #TitleCo-InventorsDateApprox Value ⓘ
7786749 Programmable integrated circuit having built in test circuit Tsung-Lu Syu 2010-08-31
7460528 Processing data packets at a storage service module of a switch Joseph I. Chamdani, Litko Chan, Richard D. Reohr, Jr. 2008-12-02 $7,643,000
6754760 Programmable interface for a configurable system bus Brian Fox, Sridhar Krishnamurthy, Bart Reynolds, Steven Winegarden 2004-06-22 $14,473,000
6526466 Method and system for PLD swapping Scott O. Frake, James McManus, David P. Schultz 2003-02-25 $13,505,000
6459646 Bank-based configuration and reconfiguration for programmable logic in a system on a chip Fung Fung Lee, Edmond Y. Cheung 2002-10-01
6218864 Structure and method for generating a clock enable signal in a PLD Steven P. Young, Jane W. Sowards 2001-04-17 $57,440,000
6094065 Integrated circuit with field programmable and application specific logic areas Danesh Tavana, Stephen M. Trimberger 2000-07-25 $120,007,000
5883525 FPGA architecture with repeatable titles including routing matrices and logic matrices Danesh Tavana, Victor A. Holen 1999-03-16 $76,659,000
5825202 Integrated circuit with field programmable and application specific logic areas Danesh Tavana, Stephen M. Trimberger 1998-10-20 $14,707,000
5682107 FPGA architecture with repeatable tiles including routing matrices and logic matrices Danesh Tavana, Victor A. Holen 1997-10-28 $30,527,000
5675589 Programmable scan chain testing structure and method 1997-10-07 $13,379,000
5550843 Programmable scan chain testing structure and method 1996-08-27 $23,069,000
5453706 Field programmable gate array providing contention free configuration and reconfiguration 1995-09-26 $35,020,000