Issued Patents All Time
Showing 1–11 of 11 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8104012 | System and methods for reducing clock power in integrated circuits | Matthew H. Klein, Stephen M. Trimberger, James M. Simkins, Brian D. Philofsky, Subodh Gupta | 2012-01-24 |
| 7669163 | Partial configuration of a programmable gate array using a bus macro and coupling the third design | Nicolas John Camilleri | 2010-02-23 |
| 7102555 | Boundary-scan circuit used for analog and digital testing of an integrated circuit | Anthony J. Collins, David P. Schultz, Neil G. Jacobson, Bradley K. Fross | 2006-09-05 |
| 7085706 | Systems and methods of utilizing virtual input and output modules in a programmable logic device | Bradley K. Fross, Michael E. Peattie | 2006-08-01 |
| 7024651 | Partial reconfiguration of a programmable gate array using a bus macro | Nicolas John Camilleri | 2006-04-04 |
| 6732347 | Clock template for configuring a programmable gate array | Nicolas John Camilleri, Kenneth J. Stickney, Jr., Jeffrey V. Lindholm, Kevin Bixler, Raymond Kong | 2004-05-04 |
| 6685766 | Corrosion inhibitor for steel-reinforced concrete | Burkhard Standke | 2004-02-03 |
| 6462579 | Partial reconfiguration of a programmable gate array using a bus macro | Nicolas John Camilleri | 2002-10-08 |
| 6384627 | Logic block used as dynamically configurable logic function | Bradley K. Fross | 2002-05-07 |
| 6157209 | Loadable up-down counter with asynchronous reset | — | 2000-12-05 |
| 6086629 | Method for design implementation of routing in an FPGA using placement directives such as local outputs and virtual buffers | Jennifer T. Tran, F. Erich Goetting | 2000-07-11 |