| 9548103 |
Scaleable look-up table based memory |
Andy L. Lee, Lu Zhou, Aniket Kadkol |
2017-01-17 |
|
| 9473145 |
Programmable high-speed I/O interface |
Bonnie I. Wang, Chiakang Sung, Joseph Huang, Khai Nguyen |
2016-10-18 |
|
| 9166589 |
Multiple data rate interface architecture |
Chiakang Sung, Joseph Huang, Yan Chong, Bonnie I. Wang |
2015-10-20 |
$8,023,000 |
| 9123437 |
Scaleable look-up table based memory |
Andy L. Lee, Lu Zhou, Aniket Kadkol |
2015-09-01 |
$43,351,000 |
| 8829948 |
Programmable high-speed I/O interface |
Bonnie I. Wang, Chiakang Sung, Joseph Huang, Khai Nguyen |
2014-09-09 |
$7,341,000 |
| 8819607 |
Method and apparatus to minimize clock tree skew in ICs |
Yen-Fu Lin, Ling Yu, Prosenjit Mal |
2014-08-26 |
$13,321,000 |
| 8644100 |
Scaleable look-up table based memory |
Andy L. Lee, Lu Zhou, Aniket Kadkol |
2014-02-04 |
$5,430,000 |
| 8593195 |
High performance memory interface circuit architecture |
Joseph Huang, Chiakang Sung, Yan Chong, Andy L. Lee, Brian Johnson |
2013-11-26 |
$14,368,000 |
| 8575957 |
Multiple data rate interface architecture |
Chiakang Sung, Joseph Huang, Yan Chong, Bonnie I. Wang |
2013-11-05 |
$7,486,000 |
| 8487665 |
Programmable high-speed interface |
Bonnie I. Wang, Chiakang Sung, Joseph Huang, Khai Nguyen |
2013-07-16 |
$11,358,000 |
| 8305121 |
High-performance memory interface circuit architecture |
Joseph Huang, Chiakang Sung, Yan Chong, Andy L. Lee, Brian Johnson |
2012-11-06 |
$22,590,000 |
| 8098082 |
Multiple data rate interface architecture |
Chiakang Sung, Joseph Huang, Yan Chong, Bonnie I. Wang |
2012-01-17 |
$10,977,000 |
| 8064280 |
Scaleable look-up table based memory |
Andy L. Lee, Lu Zhou, Aniket Kadkol |
2011-11-22 |
$27,538,000 |
| 7969215 |
High-performance memory interface circuit architecture |
Joseph Huang, Chiakang Sung, Yan Chong, Andy L. Lee, Brian Johnson |
2011-06-28 |
$45,165,000 |
| 7859304 |
Multiple data rate interface architecture |
Chiakang Sung, Joseph Huang, Yan Chong, Bonnie I. Wang |
2010-12-28 |
$6,167,000 |
| 7812633 |
Apparatus and method for the arithmetic over-ride of look up table outputs in a programmable logic device |
Andy L. Lee, David Lewis, James Schleicher |
2010-10-12 |
$5,326,000 |
| 7768430 |
Look-up table based memory |
Andy L. Lee |
2010-08-03 |
$7,125,000 |
| 7725755 |
Self-compensating delay chain for multiple-date-rate interfaces |
Yan Chong, Chiakang Sung, Bonnie I. Wang, Joseph Huang, Xiaobao Wang +1 more |
2010-05-25 |
$3,835,000 |
| 7710149 |
Input buffer for multiple differential I/O standards |
Jonathan Chung, In Whan Kim, Chiakang Sung, Bonnie I. Wang, Xiabao Wang +5 more |
2010-05-04 |
$7,278,000 |
| 7656191 |
Distributed memory in field-programmable gate array integrated circuit devices |
David Lewis, Paul Leventis, Vaughn Betz, Thomas Yau-Tsun Wong, Andy L. Lee |
2010-02-02 |
$7,193,000 |
| 7586341 |
Programmable high-speed interface |
Bonnie Wang, Chiakang Sung, Joseph Huang, Khai Nguyen |
2009-09-08 |
$3,731,000 |
| 7535275 |
High-performance memory interface circuit architecture |
Joseph Huang, Chiakang Sung, Yan Chong, Andy L. Lee, Brian Johnson |
2009-05-19 |
$41,987,000 |
| 7487415 |
Memory circuitry with data validation |
— |
2009-02-03 |
$8,260,000 |
| 7477074 |
Multiple data rate interface architecture |
Chiakang Sung, Joseph Huang, Yan Chong, Bonnie I. Wang |
2009-01-13 |
$22,275,000 |
| 7460431 |
Implementation of double data rate embedded memory in programmable devices |
Andy L. Lee |
2008-12-02 |
$8,569,000 |
