Issued Patents All Time
Showing 26–50 of 90 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8122275 | Write-leveling implementation in programmable logic devices | Bonnie I. Wang, Chiakang Sung, Joseph Huang, Michael H. M. Chu | 2012-02-21 |
| 8098082 | Multiple data rate interface architecture | Philip Pan, Chiakang Sung, Joseph Huang, Bonnie I. Wang | 2012-01-17 |
| 7990783 | Postamble timing for DDR memories | Philip Clarke, Andrew Bellis, Joseph Huang, Michael H. M. Chu | 2011-08-02 |
| 7990786 | Read-leveling implementations for DDR3 applications on an FPGA | Michael H. M. Chu, Joseph Huang, Chiakang Sung, Andrew Bellis, Philip Clarke +1 more | 2011-08-02 |
| 7983094 | PVT compensated auto-calibration scheme for DDR3 | Manoj B. Roge, Andrew Bellis, Philip Clarke, Joseph Huang, Michael H. M. Chu | 2011-07-19 |
| 7969215 | High-performance memory interface circuit architecture | Joseph Huang, Chiakang Sung, Philip Pan, Andy L. Lee, Brian Johnson | 2011-06-28 |
| 7928770 | I/O block for high performance memory interfaces | Andrew Bellis, Philip Clarke, Joseph Huang, Michael H. M. Chu, Manoj B. Roge | 2011-04-19 |
| 7898296 | Distribution and synchronization of a divided clock signal | Ning Xue, Philip Clarke, Joseph Huang | 2011-03-01 |
| 7893739 | Techniques for providing multiple delay paths in a delay circuit | Pradeep Nagarajan, Chiakang Sung, Joseph Huang | 2011-02-22 |
| 7884619 | Method and apparatus for minimizing skew between signals | Joseph Huang, Chiakang Sung, Eric Choong-Yin Chang, Peter Boyle, Adam Wright | 2011-02-08 |
| 7876630 | Postamble timing for DDR memories | Philip Clarke, Andrew Bellis, Joseph Huang, Michael H. M. Chu | 2011-01-25 |
| 7859304 | Multiple data rate interface architecture | Philip Pan, Chiakang Sung, Joseph Huang, Bonnie I. Wang | 2010-12-28 |
| 7746134 | Digitally controlled delay-locked loops | Sean Shau-Tu Lu, Chiakang Sung, Joseph Huang | 2010-06-29 |
| 7725755 | Self-compensating delay chain for multiple-date-rate interfaces | Chiakang Sung, Bonnie I. Wang, Joseph Huang, Xiaobao Wang, Philip Pan +1 more | 2010-05-25 |
| 7710149 | Input buffer for multiple differential I/O standards | Jonathan Chung, In Whan Kim, Philip Pan, Chiakang Sung, Bonnie I. Wang +5 more | 2010-05-04 |
| 7706996 | Write-side calibration for data interface | Chiakang Sung, Joseph Huang, Michael H. M. Chu | 2010-04-27 |
| 7671579 | Method and apparatus for quantifying and minimizing skew between signals | Joseph Huang, Chiakang Sung, Eric Choong-Yin Chang, Peter Boyle, Adam Wright | 2010-03-02 |
| 7642812 | Distribution and synchronization of a divided clock signal | Ning Xue, Philip Clarke, Joseph Huang | 2010-01-05 |
| 7593273 | Read-leveling implementations for DDR3 applications on an FPGA | Michael H. M. Chu, Joseph Huang, Chiakang Sung, Andrew Bellis, Philip Clarke +1 more | 2009-09-22 |
| 7589556 | Dynamic control of memory interface timing | Johnson Tan, Andrew Bellis, Philip Clarke, Joseph Huang, Michael H. M. Chu +1 more | 2009-09-15 |
| 7590008 | PVT compensated auto-calibration scheme for DDR3 | Manoj B. Roge, Andrew Bellis, Philip Clarke, Joseph Huang, Michael H. M. Chu | 2009-09-15 |
| 7535275 | High-performance memory interface circuit architecture | Joseph Huang, Chiakang Sung, Philip Pan, Andy L. Lee, Brian Johnson | 2009-05-19 |
| 7509223 | Read-side calibration for data interface | Chiakang Sung, Joseph Huang, Michael H. M. Chu | 2009-03-24 |
| 7492185 | Innovated technique to reduce memory interface write mode SSN in FPGA | Joseph Huang, Chiakang Sung, Michael H. M. Chu | 2009-02-17 |
| 7477074 | Multiple data rate interface architecture | Philip Pan, Chiakang Sung, Joseph Huang, Bonnie I. Wang | 2009-01-13 |