| 11138126 |
Testing hierarchical address translation with context switching and overwritten table definition data |
— |
2021-10-05 |
| 10084591 |
SERDES built-in sinusoidal jitter injection |
Chaitanya Palusa, Dawei Huang, Jiangyuan Li |
2018-09-25 |
| 9711189 |
On-die input reference voltage with self-calibrating duty cycle correction |
Bonnie I. Wang, Chiakang Sung, Xiaobao Wang, Yan Chong, Joseph Huang +1 more |
2017-07-18 |
| 9158873 |
Circuit design technique for DQS enable/disable calibration |
Yan Chong, Joseph Huang, Sean Shau-Tu Lu, Chiakang Sung |
2015-10-13 |
| 9059716 |
Digital PVT compensation for delay chain |
Yan Chong, Sean Shau-Tu Lu, Chiakang Song, Joseph Huang |
2015-06-16 |
| 8847626 |
Circuits and methods for providing clock signals |
Yan Chong, Warren Nordyke, James Lin, Weiqi Ding |
2014-09-30 |
| 8787097 |
Circuit design technique for DQS enable/disable calibration |
Yan Chong, Joseph Huang, Sean Shau-Tu Lu, Chiakang Sung |
2014-07-22 |
| 8680905 |
Digital PVT compensation for delay chain |
Yan Chong, Sean Shau-Tu Lu, Chiakang Sung, Joseph Huang |
2014-03-25 |
| 8624647 |
Duty cycle correction circuit for memory interfaces in integrated circuits |
Yan Chong, Joseph Huang, Chiakang Sung |
2014-01-07 |
| 8565034 |
Variation compensation circuitry for memory interface |
Sean Shau-Tu Lu, Joseph Huang, Yan Chong, Chiakang Sung |
2013-10-22 |
| 8237475 |
Techniques for generating PVT compensated phase offset to improve accuracy of a locked loop |
Sean Shau-Tu Lu, Chiakang Sung, Joseph Huang, Yan Chong |
2012-08-07 |
| 8159277 |
Techniques for providing multiple delay paths in a delay circuit |
Yan Chong, Chiakang Sung, Joseph Huang |
2012-04-17 |
| 8130016 |
Techniques for providing reduced duty cycle distortion |
Yan Chong, Chiakang Sung, Joseph Huang |
2012-03-06 |
| 7893739 |
Techniques for providing multiple delay paths in a delay circuit |
Yan Chong, Chiakang Sung, Joseph Huang |
2011-02-22 |
