CP

Chaitanya Palusa

TSMC: 7 patents #3,492 of 12,232Top 30%
AP Avago Technologies General Ip (Singapore) Pte.: 6 patents #139 of 2,004Top 7%
Oracle: 6 patents #2,063 of 14,854Top 15%
LS Lsi: 5 patents #274 of 1,740Top 20%
AS Alliance Semiconductor: 3 patents #12 of 32Top 40%
Lsi Logic: 2 patents #799 of 1,957Top 45%
📍 San Jose, CA: #2,096 of 32,062 inventorsTop 7%
🗺 California: #17,896 of 386,348 inventorsTop 5%
Overall (All Time): #128,257 of 4,157,543Top 4%
29
Patents All Time

Issued Patents All Time

Showing 1–25 of 29 patents

Patent #TitleCo-InventorsDate
12335074 Multi-tap decision feed-forward equalizer with precursor and postcursor taps Rob Abbott, Wei-Li Chen, Po-Hsiang Lan, Dirk Pfaff, Cheng-Hsiang Hsieh 2025-06-17
12074737 SerDes receiver with optimized CDR pulse shaping Rob Abbott, Rolando Solano Ramirez, Wei-Li Chen, Dirk Pfaff, Cheng-Hsiang Hsieh +1 more 2024-08-27
11962441 Multi-tap decision feed-forward equalizer with precursor and postcursor taps Rob Abbott, Wei-Li Chen, Po-Hsiang Lan, Dirk Pfaff, Cheng-Hsiang Hsieh 2024-04-16
11784855 Adaptive receiver with pre-cursor cancelation Xun Zhang, Dawei Huang, Muthukumar Vairavan, Jianghui Su 2023-10-10
11558223 Adaptive receiver with pre-cursor cancelation Xun Zhang, Dawei Huang, Muthukumar Vairavan, Jianghui Su 2023-01-17
11398933 Multi-tap decision feed-forward equalizer with precursor and postcursor taps Rob Abbott, Wei-Li Chen, Po-Hsiang Lan, Dirk Pfaff, Cheng-Hsiang Hsieh 2022-07-26
11240075 SerDes receiver with optimized CDR pulse shaping Rob Abbott, Rolando Solano Ramirez, Wei-Li Chen, Dirk Pfaff, Cheng-Hsiang Hsieh +1 more 2022-02-01
11240073 Adapative receiver with pre-cursor cancelation Xun Zhang, Dawei Huang, Muthukumar Vairavan, Jianghui Su 2022-02-01
10911272 Multi-tap decision feed-forward equalizer with precursor and postcursor taps Rob Abbott, Wei-Li Chen, Po-Hsiang Lan, Dirk Pfaff, Cheng-Hsiang Hsieh 2021-02-02
10904044 Serdes receiver with optimized CDR pulse shaping Rob Abbott, Rolando Solano Ramirez, Wei-Li Chen, Dirk Pfaff, Cheng-Hsiang Hsieh +1 more 2021-01-26
10142089 Baud-rate clock data recovery with improved tracking performance Yuhan Yao, Xun Zhang, Dawei Huang, Jianghui Su, Muthukumar Vairavan 2018-11-27
10084591 SERDES built-in sinusoidal jitter injection Dawei Huang, Jiangyuan Li, Pradeep Nagarajan 2018-09-25
9917607 Baseline wander correction gain adaptation Xun Zhang, Dawei Huang, Jianghui Su 2018-03-13
9385893 Modular low power serializer-deserializer Tomasz Prokop, Hiep T. Pham, Volodymyr Shvydun, Adam B. Healey 2016-07-05
9304535 Baud rate phase detector with no error latches Volodymyr Shvydun, Adam B. Healey, Hiep T. Pham 2016-04-05
9215106 Method and apparatus for pre-cursor intersymbol interference correction Adam B. Healey, Hiep T. Pham, Volodymyr Shvydun 2015-12-15
9130797 Pipelined decision feedback equalization in an interleaved serializer/deserializer receiver Volodymyr Shvydun, Hiep T. Pham, Adam B. Healey 2015-09-08
9077574 DSP SerDes receiver with FFE-DFE-DFFE data path Adam B. Healey, Tomasz Prokop, Volodymyr Shvydun 2015-07-07
9036729 Code forwarding and clock generation for transmitter repeaters Hiep T. Pham, Tomasz Prokop, Adam B. Healey 2015-05-19
8976854 Method and apparatus for feed forward equalizer with variable cursor position Adam B. Healey, Tomasz Prokop, Volodymyr Shvydun 2015-03-10
8804889 Receiver with dual clock recovery circuits Tomasz Prokop 2014-08-12
8787439 Decision feedforward equalization Tomasz Prokop, Adam B. Healey, Ye Liu 2014-07-22
8582635 Sparse and reconfigurable floating tap feed forward equalization Tomasz Prokop 2013-11-12
8508308 Automatic frequency calibration of a multi-LCVCO phase locked loop with adaptive thresholds and programmable center control voltage Yikui Jen Dong, Freeman Y. Zhong, Tai Jing 2013-08-13
7027548 Delay settings for a wide-range, high-precision delay-locked loop and a delay locked loop implementation using these settings Abhijit Ray 2006-04-11