Issued Patents All Time
Showing 1–25 of 26 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12401346 | Efficient architecture for high-performance DSP-based long-reach SERDES | Magesh Valliappan | 2025-08-26 |
| 11689395 | Efficient architecture for high-performance DSP-based SERDES | Magesh Valliappan | 2023-06-27 |
| 10715356 | High-speed interconnect solutions with support for secondary continuous time in-band back channel communication for simplex retimer solutions | Magesh Valliappan | 2020-07-14 |
| 10560555 | High-speed interconnect solutions with support for co-propagating and counter-propagating continuous time back channel communication | — | 2020-02-11 |
| 10530906 | High-speed interconnect solutions with support for continuous time back channel communication | — | 2020-01-07 |
| 10511549 | High-speed interconnect solutions with support for continuous time in-band back channel communication and proprietary features | — | 2019-12-17 |
| 9385893 | Modular low power serializer-deserializer | Chaitanya Palusa, Tomasz Prokop, Hiep T. Pham, Volodymyr Shvydun | 2016-07-05 |
| 9304535 | Baud rate phase detector with no error latches | Volodymyr Shvydun, Chaitanya Palusa, Hiep T. Pham | 2016-04-05 |
| 9215106 | Method and apparatus for pre-cursor intersymbol interference correction | Chaitanya Palusa, Hiep T. Pham, Volodymyr Shvydun | 2015-12-15 |
| 9130797 | Pipelined decision feedback equalization in an interleaved serializer/deserializer receiver | Chaitanya Palusa, Volodymyr Shvydun, Hiep T. Pham | 2015-09-08 |
| 9077574 | DSP SerDes receiver with FFE-DFE-DFFE data path | Chaitanya Palusa, Tomasz Prokop, Volodymyr Shvydun | 2015-07-07 |
| 9036729 | Code forwarding and clock generation for transmitter repeaters | Hiep T. Pham, Chaitanya Palusa, Tomasz Prokop | 2015-05-19 |
| 8976854 | Method and apparatus for feed forward equalizer with variable cursor position | Tomasz Prokop, Volodymyr Shvydun, Chaitanya Palusa | 2015-03-10 |
| 8902959 | System and method for determining channel loss in a dispersive communication channel at the Nyquist frequency | Viswanath Annampedu, Amaresh V. Malipatil | 2014-12-02 |
| 8860467 | Biased bang-bang phase detector for clock and data recovery | Amaresh V. Malipatil, Sunil Srinivasa, Pervez M. Aziz | 2014-10-14 |
| 8787439 | Decision feedforward equalization | Chaitanya Palusa, Tomasz Prokop, Ye Liu | 2014-07-22 |
| 8687682 | Transmitter adaptation loop using adjustable gain and convergence detection | Mohammad S. Mobin, Amaresh V. Malipatil, Ye Liu | 2014-04-01 |
| 8467440 | Compensated phase detector for generating one or more clock signals using DFE detected data in a receiver | Pervez M. Aziz | 2013-06-18 |
| 8379711 | Methods and apparatus for decision-feedback equalization with oversampled phase detector | Pervez M. Aziz, Amaresh V. Malipatil, Lizhi Zhong | 2013-02-19 |
| 8279950 | Compensation for transmission line length variation in a SERDES system | Pervez M. Aziz, Shawn M. Logan | 2012-10-02 |
| 8085837 | Characterizing non-compensable jitter in an electronic signal | Mark J. Marlett | 2011-12-27 |
| 8054892 | Compensating transmission line to reduce sensitivity of performance due to channel length variation | Pervez M. Aziz, Shawn M. Logan | 2011-11-08 |
| 8040984 | Methods and apparatus for improved jitter tolerance in an SFP limit amplified signal | Pervez M. Aziz, Mohammad S. Mobin, Gary E. Schiessler, Gregory W. Sheets, Lane A. Smith +2 more | 2011-10-18 |
| 7813285 | Method for per-port flow control of packets aggregated from multiple logical ports over a transport link | Mark A. Bordogna, Sundararajan Cidambara | 2010-10-12 |
| 7593327 | Method and apparatus for frequency offset control of ethernet packets over a transport network | Mark A. Bordogna, Peter A. Stropparo | 2009-09-22 |