PA

Pervez M. Aziz

AS Agere Systems: 32 patents #12 of 1,849Top 1%
LS Lsi: 13 patents #73 of 1,740Top 5%
NV NVIDIA: 9 patents #816 of 7,811Top 15%
AP Avago Technologies General Ip (Singapore) Pte.: 6 patents #139 of 2,004Top 7%
Overall (All Time): #38,752 of 4,157,543Top 1%
60
Patents All Time

Issued Patents All Time

Showing 25 most recent of 60 patents

Patent #TitleCo-InventorsDate
12267210 Adapting forward error correction (FEC) or link parameters for improved post-FEC performance Vishnu Balan, Rohit Rathi 2025-04-01
11985220 Equalization adaptation schemes for high-speed links Vishnu Balan, Mohammad S. Mobin, Akshay Shyam Pavagada Raghavendra 2024-05-14
11665029 Feed forward filter equalizer adaptation using a constrained filter tap coefficient value Vishnu Balan, Guo-Hau Gau 2023-05-30
11646863 Equalization adaptation schemes for high-speed links Vishnu Balan, Mohammad S. Mobin, Akshay Shyam Pavagada Raghavendra 2023-05-09
11611458 Decision feed forward equalization for intersymbol interference cancelation Vishnu Balan, Viswanath Annampedu 2023-03-21
11477004 Clock data recovery convergence in modulated partial response systems Vishnu Balan, Viswanath Annampedu 2022-10-18
11212073 Clock data recovery convergence using signed timing injection Vishnu Balan, Viswanath Annampedu 2021-12-28
11159304 Clock data recovery mechanism Rohit Rathi, Vishnu Balan 2021-10-26
10700846 Clock data recovery convergence using signed timing injection Vishnu Balan, Viswanath Annampedu 2020-06-30
9397674 Clock recovery using quantized phase error samples using jitter frequency-dependent quantization thresholds and loop gains Shiva Prasad Kotagiri, Sundeep Venkatraman, Sunil Srinivasa, Amaresh V. Malipatil 2016-07-19
9294314 Receiver having limiter-enhanced data eye openings Mohammad S. Mobin, Ye Liu 2016-03-22
9143367 Clock and data recovery architecture with adaptive digital phase skew Amaresh V. Malipatil, Viswanath Annampedu 2015-09-22
9106462 Reduced power SERDES receiver using selective adaptation of equalizer parameters in response to supply voltage and operating temperature variations and technique for measuring same Amaresh V. Malipatil, Mohammad S. Mobin 2015-08-11
9106370 Enhanced clock and data recovery acquisition in the presence of large frequency offsets Sunil Srinivasa, Amaresh V. Malipatil, Mohammad S. Mobin, Shiva Prasad Kotagiri 2015-08-11
8908816 Receiver with distortion compensation circuit Hiroshi Kimura 2014-12-09
8902963 Methods and apparatus for determining threshold of one or more DFE transition latches based on incoming data eye Mohammad S. Mobin 2014-12-02
8860467 Biased bang-bang phase detector for clock and data recovery Amaresh V. Malipatil, Sunil Srinivasa, Adam B. Healey 2014-10-14
8837626 Conditional adaptation of linear filters in a system having nonlinearity Amaresh V. Malipatil, Mohammad S. Mobin, Ye Liu 2014-09-16
8831142 Adaptive cancellation of voltage offset in a communication system Shiva Prasad Kotagiri, Amaresh V. Malipatil 2014-09-09
8761237 Low nonlinear distortion variable gain amplifier Hiroshi Kimura 2014-06-24
8743945 Shift register based downsampled floating tap decision feedback equalization Hiroshi Kimura, Amaresh V. Malipatil, Hairong Gao 2014-06-03
8737549 Receiver having limiter-enhanced data eye openings Mohammad S. Mobin, Ye Liu 2014-05-27
8731040 Adapting transfer functions of continuous-time equalizers Amaresh V. Malipatil 2014-05-20
8705672 Method of compensating for nonlinearity in a DFE-based receiver Amaresh V. Malipatil, Mohammad S. Mobin, Ye Liu 2014-04-22
8548038 Pattern detector for serializer-deserializer adaptation Vladimir Sindalovsky, Mohammad S. Mobin, Lane A. Smith, Amaresh V. Malipatil 2013-10-01