MB

Mark A. Bordogna

IN Intel: 14 patents #2,910 of 30,777Top 10%
AT AT&T: 8 patents #2,286 of 18,772Top 15%
AS Agere Systems: 3 patents #475 of 1,849Top 30%
Overall (All Time): #157,681 of 4,157,543Top 4%
25
Patents All Time

Issued Patents All Time

Patent #TitleCo-InventorsDate
12222750 Timestamp alignment across multiple computing nodes Jonathan A. Robinson 2025-02-11
12177003 Method and apparatus for data plane control of network time sync protocol in multi-host systems Srinivasan S. IYENGAR 2024-12-24
12160495 Timestamp alignment for multiple nodes Jonathan A. Robinson, Srinivasan S. IYENGAR 2024-12-03
11805042 Technologies for timestamping with error correction Yoni Landau, Janardhan H. Satyanarayana, Assaf Benhamou 2023-10-31
11711159 High accuracy time stamping for multi-lane ports Janardhan H. Satyanarayana, Yoni Landau, Diwakar Suvvari 2023-07-25
11693448 Timestamp alignment across multiple computing nodes Jonathan A. Robinson 2023-07-04
11671194 Technologies for high-precision timestamping of packets Janardhan H. Satyanarayana, Larry N. Wakeman, Robert Southworth, Mika Nystroem 2023-06-06
11546241 Technologies for timestamping with error correction Yoni Landau, Janardhan H. Satyanarayana, Assaf Benhamou 2023-01-03
11265096 High accuracy time stamping for multi-lane ports Janardhan H. Satyanarayana, Yoni Landau, Diwakar Suvvari 2022-03-01
11212024 Technologies for high-precision timestamping of packets Janardhan H. Satyanarayana, Larry N. Wakeman, Robert Southworth, Mika Nystroem 2021-12-28
11153191 Technologies for timestamping with error correction Yoni Landau, Janardhan H. Satyanarayana, Assaf Benhamou 2021-10-19
10931391 One-step time stamping of synchronization packets for networked devices Sita Rama Chandrasekhar Mallela 2021-02-23
10509435 Protected real time clock with hardware interconnects Ramamurthy Krithivas, James M. Sepko 2019-12-17
9065761 Packet reassembly processing Robert J. Munoz 2015-06-23
8005094 Method and apparatus for circuit emulation services over cell and packet networks Juergen Beck, Christopher W. Hamilton 2011-08-23
7813285 Method for per-port flow control of packets aggregated from multiple logical ports over a transport link Sundararajan Cidambara, Adam B. Healey 2010-10-12
7593327 Method and apparatus for frequency offset control of ethernet packets over a transport network Adam B. Healey, Peter A. Stropparo 2009-09-22
6683855 Forward error correction for high speed optical transmission systems Ralf Dohmen, Wolfram Sturm 2004-01-27
6560202 Control architecture using a multi-layer embedded signal status protocol Philip Sidney Dietz, Joseph Elide Landry, Jeffrey Robert Towne, Warren Clifton Trested, Jr. 2003-05-06
6366556 Self-healing networks using virtual rings James E. Ballintine, Wilhelm Kremer 2002-04-02
6301228 Method and apparatus for switching signals using an embedded group signal status Philip Sidney Dietz, Joseph Elide Landry, Jeffrey Robert Towne, Warren Clifton Trested, Jr. 2001-10-09
6137790 Control architecture for a homogeneous routing structure Philip Sidney Dietz, Joseph Elide Landry, Jeffrey Robert Towne, Warren Clifton Trested, Jr. 2000-10-24
6091731 Duplication in asychronous transfer mode (ATM) network fabrics Janus Biegaj, Mark H. Davis, Dominic Dominijanni, Kurt A. Hedlund, Gary Lynn McElvany 2000-07-18
6091730 Control of asynchronous transfer mode (ATM) switching networks Janus Biegaj, Mark H. Davis, Dominic Dominijani, Kurt A. Hedlund, Gary Lynn McElvany 2000-07-18
6081503 Control architecture using an embedded signal status protocol Philip Sidney Dietz, Joseph Elide Landry, Jeffrey Robert Towne, Warren Clifton Trested, Jr. 2000-06-27