Issued Patents All Time
Showing 1–8 of 8 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11805042 | Technologies for timestamping with error correction | Janardhan H. Satyanarayana, Assaf Benhamou, Mark A. Bordogna | 2023-10-31 |
| 11711159 | High accuracy time stamping for multi-lane ports | Mark A. Bordogna, Janardhan H. Satyanarayana, Diwakar Suvvari | 2023-07-25 |
| 11546241 | Technologies for timestamping with error correction | Janardhan H. Satyanarayana, Assaf Benhamou, Mark A. Bordogna | 2023-01-03 |
| 11265096 | High accuracy time stamping for multi-lane ports | Mark A. Bordogna, Janardhan H. Satyanarayana, Diwakar Suvvari | 2022-03-01 |
| 11190208 | Techniques for link partner error reporting | Adee O. Ran, Amir Mezer, Alon Meisler, Assaf Benhamou, Itamar Levin | 2021-11-30 |
| 11153191 | Technologies for timestamping with error correction | Janardhan H. Satyanarayana, Assaf Benhamou, Mark A. Bordogna | 2021-10-19 |
| 10924132 | Techniques for link partner error reporting | Adee O. Ran, Amir Mezer, Alon Meisler, Assaf Benhamou, Itamar Levin | 2021-02-16 |
| 9722717 | Technologies for ethernet link robustness for deep sleep low power applications | Assaf Benhamou, Adee O. Ran | 2017-08-01 |