Issued Patents All Time
Showing 51–75 of 90 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7425844 | Input buffer for multiple differential I/O standards | Jonathan Chung, In Whan Kim, Philip Pan, Chiakang Sung, Bonnie I. Wang +5 more | 2008-09-16 |
| 7330051 | Innovated technique to reduce memory interface write mode SSN in FPGA | Joseph Huang, Chiakang Sung, Michael H. M. Chu | 2008-02-12 |
| 7324405 | DQS postamble filtering | Sanjay K. Charagulla, Chiakang Sung, Joseph Huang, Bonnie I. Wang | 2008-01-29 |
| 7321518 | Apparatus and methods for providing redundancy in integrated circuits | Joseph Huang, Chiakang Sung, Philip Pan | 2008-01-22 |
| 7309906 | Apparatus and methods for providing highly effective and area efficient decoupling capacitance in programmable logic devices | Jeffrey Tyhach, Bonnie I. Wang, Chiakang Sung | 2007-12-18 |
| 7231536 | Control circuit for self-compensating delay chain for multiple-data-rate interfaces | Chiakang Sung, Joseph Huang, Philip Pan | 2007-06-12 |
| 7227395 | High-performance memory interface circuit architecture | Joseph Huang, Chiakang Sung, Philip Pan, Andy L. Lee, Brian Johnson | 2007-06-05 |
| 7215143 | Input buffer for multiple differential I/O standards | Jonathan Chung, In Whan Kim, Philip Pan, Chiakang Sung, Bonnie I. Wang +5 more | 2007-05-08 |
| 7212054 | DLL with adjustable phase shift using processed control signal | Tzung-Chin Chang, Chiakang Sung, Henry Kim, Joseph Huang | 2007-05-01 |
| 7205802 | Apparatus and method for controlling a delay chain | Bonnie I. Wang, Joseph Huang, Chiakang Sung, Khai Nguyen, Henry Kim | 2007-04-17 |
| 7205806 | Loop circuitry with low-pass noise filter | Joseph Huang, Chiakang Sung, Philip Pan, Tzung-Chin Chang | 2007-04-17 |
| 7200769 | Self-compensating delay chain for multiple-date-rate interfaces | Chiakang Sung, Bonnie I. Wang, Joseph Huang, Xiaobao Wang, Philip Pan +1 more | 2007-04-03 |
| 7167023 | Multiple data rate interface architecture | Philip Pan, Chiakang Sung, Joseph Huang, Bonnie I. Wang | 2007-01-23 |
| 7119579 | Supply voltage detection circuit | Chiakang Sung, Bonnie I. Wang, Khai Nguyen, Joseph Huang, Xiaobao Wang +6 more | 2006-10-10 |
| 7098690 | Programmable I/O element circuit for high speed logic devices | Khai Nguyen, Chiakang Sung, Bonnie I. Wang, Joseph Huang, Phillip Pan +4 more | 2006-08-29 |
| 7091760 | DLL with adjustable phase shift using processed control signal | Tzung-Chin Chang, Chiakang Sung, Henry Kim, Joseph Huang | 2006-08-15 |
| 7057962 | Address control for efficient memory partition | Johnson Tan, Chiakang Sung, Philip Pan, Joseph Huang | 2006-06-06 |
| 7030675 | Apparatus and method for controlling a delay chain | Bonnie I. Wang, Joseph Huang, Chiakang Sung, Khai Nguyen, Henry Kim | 2006-04-18 |
| 7031222 | DQS postamble filtering | Sanjay K. Charagulla, Chiakang Sung, Joseph Huang, Bonnie I. Wang | 2006-04-18 |
| 7002384 | Loop circuitry with low-pass noise filter | Joseph Huang, Chiakang Sung, Philip Pan, Tzung-Chin Chang | 2006-02-21 |
| 6992947 | Dual-port SRAM in a programmable logic device | Philip Pan, Chiakang Sung, Joseph Huang, Bonnie I. Wang, Khai Nguyen +3 more | 2006-01-31 |
| 6961280 | Techniques for implementing address recycling in memory circuits | Philip Pan, Chiakang Sung, Joseph Huang, Johnson Tan | 2005-11-01 |
| 6946872 | Multiple data rate interface architecture | Philip Pan, Chiakang Sung, Joseph Huang, Bonnie I. Wang | 2005-09-20 |
| 6912164 | Techniques for preloading data into memory on programmable circuits | Chiakang Sung, Joseph Huang, Philip Pan, Johnson Tan | 2005-06-28 |
| 6911860 | On/off reference voltage switch for multiple I/O standards | Xiaobao Wang, Chiakang Sung, Khai Nguyen, Joseph Huang, Bonnie I. Wang +4 more | 2005-06-28 |