Issued Patents All Time
Showing 25 most recent of 26 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11281195 | Integrated circuits with in-field diagnostic and repair capabilities | Kenneth T. Daxer, Gregory Steinke, Kalyana Ravindra Kantipudi | 2022-03-22 |
| 9171253 | Identifying predictive models resistant to concept drift | Sourabh Satish, Jeffrey Wilhelm | 2015-10-27 |
| 8800030 | Individualized time-to-live for reputation scores of computer files | Vijay Seshadri, Zulfikar Ramzan, James Hoagland, Adam Glick | 2014-08-05 |
| 8786301 | Apparatus for a low-cost semiconductor test interface system | Joseph W. Foerstel, Mark Andrew Banke, Ken Ito | 2014-07-22 |
| 8779754 | Method and apparatus for minimizing skew between signals | Yan Chong, Joseph Huang, Chiakang Sung, Eric Choong-Yin Chang, Peter Boyle | 2014-07-15 |
| 8701190 | Inferring file and website reputations by belief propagation leveraging machine reputation | Duen Hong Chau | 2014-04-15 |
| 8543876 | Method and apparatus for serial scan test data delivery | — | 2013-09-24 |
| 8341745 | Inferring file and website reputations by belief propagation leveraging machine reputation | Duen Horng Chau | 2012-12-25 |
| 7940082 | Circuits and method for bypassing a static configuration in a programmable logic device to implement a dynamic multiplexer | — | 2011-05-10 |
| 7884619 | Method and apparatus for minimizing skew between signals | Yan Chong, Joseph Huang, Chiakang Sung, Eric Choong-Yin Chang, Peter Boyle | 2011-02-08 |
| 7795909 | High speed programming of programmable logic devices | Kenneth T. Daxer | 2010-09-14 |
| 7768280 | Apparatus for a low-cost semiconductor test interface system | Joseph W. Foerstel, Mark Andrew Banke, Ken Ito | 2010-08-03 |
| 7685485 | Functional failure analysis techniques for programmable integrated circuits | Binh Vo, Wan-Pin Hung, David Huang, Peter Boyle, Qi Richard Chen +4 more | 2010-03-23 |
| 7671579 | Method and apparatus for quantifying and minimizing skew between signals | Yan Chong, Joseph Huang, Chiakang Sung, Eric Choong-Yin Chang, Peter Boyle | 2010-03-02 |
| 7546507 | Method and apparatus for debugging semiconductor devices | Daniel L. Reilly, Yoke Mooi Lee | 2009-06-09 |
| 7409669 | Automatic test configuration generation facilitating repair of programmable circuits | Jayabrata Ghosh Dastidar, Paul Tracy | 2008-08-05 |
| 7265573 | Methods and structures for protecting programming data for a programmable logic device | — | 2007-09-04 |
| 7237106 | System for loading configuration data into a configuration word register by independently loading a plurality of configuration blocks through a plurality of configuration inputs | Paul Tracy | 2007-06-26 |
| 7103813 | Method and apparatus for testing interconnect bridging faults in an FPGA | Paul Tracy, Anthony Pang, Andy L. Lee, Rahul Saini | 2006-09-05 |
| 7024327 | Techniques for automatically generating tests for programmable circuits | Jayabrata Ghosh Dastidar, Hung Hing Anthony Pang, Binh Vo, Ajay Nagarandal, Paul Tracy +1 more | 2006-04-04 |
| 7020582 | Methods and apparatus for laser marking of integrated circuit faults | John DiCosola, Junzhao Lei, Mark Andrew Banke, William H Hata | 2006-03-28 |
| 6938236 | Method of creating a mask-programmed logic device from a pre-existing circuit design | Jonathan Park, Eugen Chen, Richard C. Saito, Evgueni Ratchev | 2005-08-30 |
| 6625771 | Tool to reconfigure pin connections between a DUT and a tester | — | 2003-09-23 |
| 6247155 | Tool to reconfigure pin connections between a DUT and a tester | — | 2001-06-12 |
| 6112020 | Apparatus and method for generating configuration and test files for programmable logic devices | — | 2000-08-29 |