Issued Patents All Time
Showing 1–17 of 17 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9811628 | Metal configurable register file | Yau Kok Lai, Teck Siong Ong, Yin Hao Liew | 2017-11-07 |
| 9590634 | Metal configurable hybrid memory | Yau Kok Lai, Teck Siong Ong, Yin Hao Liew | 2017-03-07 |
| 9577640 | Flexible, space-efficient I/O circuitry for integrated circuits | Yin Hao Liew, Kok Seong Lee, Salah M Werfelli | 2017-02-21 |
| 9166593 | Flexible, space-efficient I/O circuitry for integrated circuits | Yin Hao Liew, Kok Seong Lee, Salah M Werfelli | 2015-10-20 |
| 8788984 | Gate array architecture with multiple programmable regions | Salah M Werfelli, WeiZhi Kang, Wan Tat Hooi, Kok Siong Tee, Jeremy Jia Jian Lee | 2014-07-22 |
| 8773163 | Flexible, space-efficient I/O circuitry for integrated circuits | Yin Hao Liew, Kok Seong Lee, Salah M Werfelli | 2014-07-08 |
| 8533641 | Gate array architecture with multiple programmable regions | Salah M Werfelli, WeiZhi Kang, Wan Tat Hooi, Kok Siong Tee, Jeremy Jia Jian Lee | 2013-09-10 |
| 8339844 | Programmable vias for structured ASICs | Herman Schmit, Ronnie Vasishta, Adam E. Levinthal | 2012-12-25 |
| 8001509 | Method for programming a mask-programmable logic device and device so programmed | Steven Perry, Gregor Nixon, Larry Kong, Alasdair Scott, Andrew Hall +3 more | 2011-08-16 |
| 7759971 | Single via structured IC device | Shu Ern Perng Mark, Yit Ping Kok, Soon Chieh Lim, Herman Schmit | 2010-07-20 |
| 7689960 | Programmable via modeling | Yit Ping Kok, Soon Chieh Lim, Yin Hao Liew, Wai Leng Chek | 2010-03-30 |
| 7290237 | Method for programming a mask-programmable logic device and device so programmed | Steven Perry, Gregor Nixon, Larry Kong, Alasdair Scott, Andrew Hall +3 more | 2007-10-30 |
| 7165230 | Switch methodology for mask-programmable logic devices | — | 2007-01-16 |
| 6938236 | Method of creating a mask-programmed logic device from a pre-existing circuit design | Eugen Chen, Richard C. Saito, Adam Wright, Evgueni Ratchev | 2005-08-30 |
| 6886143 | Method and apparatus for providing clock/buffer network in mask-programmable logic device | — | 2005-04-26 |
| 6742172 | Mask-programmable logic devices with programmable gate array sites | — | 2004-05-25 |
| 5990502 | High density gate array cell architecture with metallization routing tracks having a variable pitch | — | 1999-11-23 |