Ram Huggahalli — 14 Patents at Intel

Ram Huggahalli has been granted 14 US patents while listed as an inventor at Intel. The first was granted in 2004 and the most recent in July 2021. Ram Huggahalli ranks #332,869 of 4,157,543 US inventors in our database (top 8.0%). Patent records list Ram Huggahalli in Portland, OR, US.

Issued Patents All Time

Showing 1–14 of 14 patents

Patent #	Title	Co-Inventors	Date	Approx Value ⓘ
11068399	Technologies for enforcing coherence ordering in consumer polling interactions by receiving snoop request by controller and update value of cache line	Bin Li, Chunhui Zhang, Ren Wang	2021-07-20	$44,320,000
8751676	Message communication techniques	Steven R. King, Xia Zhu, Mazhar Memon, Frank L. Berry, Nitin Bhardwaj +2 more	2014-06-10	$19,303,000
8688868	Steering data units to a consumer	Anil Vasudevan, Partha Sarangam, Sujoy Sen	2014-04-01	$15,469,000
8645596	Interrupt techniques	Amit Kumar, Steven R. King, Xia Zhu, Mazhar Memon, Frank L. Berry +2 more	2014-02-04	$11,338,000
8307105	Message communication techniques	Steven R. King, Xia Zhu, Mazhar Memon, Frank L. Berry, Nitin Bhardwaj +2 more	2012-11-06	$14,021,000
8041854	Steering data units to a consumer	Anil Vasudevan, Partha Sarangam, Sujoy Sen	2011-10-18	$21,649,000
7996548	Message communication techniques	Steven R. King, Xia Zhu, Mazhar Memon, Frank L. Berry, Nitin Bhardwaj +2 more	2011-08-09	$24,223,000
7512750	Processor and memory controller capable of use in computing system that employs compressed cache lines' worth of information	Chris J. Newburn, Herbert Hum, Ali-Reza Adl-Tabatabai, Anwar Ghuloum	2009-03-31	$17,039,000
7502877	Dynamically setting routing information to transfer input output data directly into processor caches in a multi processor system	Raymond S. Tetrick	2009-03-10	$16,837,000
7257693	Multi-processor computing system that employs compressed cache lines' worth of information and processor capable of use in said system	Chris J. Newburn, Herbert Hum, Ali-Reza Adl-Tabatabai, Anwar Ghuloum	2007-08-14	$18,880,000
7231470	Dynamically setting routing information to transfer input output data directly into processor caches in a multi processor system	Raymond S. Tetrick	2007-06-12	$15,149,000
7185147	Striping across multiple cache lines to prevent false sharing	Ramesh Illikkal	2007-02-27	$10,067,000
7143238	Mechanism to compress data in a cache	Ali-Reza Adl-Tabatabai, Anwar Ghuloum, Chris J. Newburn	2006-11-28	$16,743,000
6785793	Method and apparatus for memory access scheduling to reduce memory access latency	Nagi Aboulenein, Randy B. Osborne, Vamsee K. Madavarapu, Ken M. Crocker	2004-08-31	$18,815,000

Ram Huggahalli — 14 Patents

Issued Patents All Time

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