Issued Patents All Time
Showing 1–14 of 14 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11068399 | Technologies for enforcing coherence ordering in consumer polling interactions by receiving snoop request by controller and update value of cache line | Bin Li, Chunhui Zhang, Ren Wang | 2021-07-20 |
| 8751676 | Message communication techniques | Steven R. King, Xia Zhu, Mazhar Memon, Frank L. Berry, Nitin Bhardwaj +2 more | 2014-06-10 |
| 8688868 | Steering data units to a consumer | Anil Vasudevan, Partha Sarangam, Sujoy Sen | 2014-04-01 |
| 8645596 | Interrupt techniques | Amit Kumar, Steven R. King, Xia Zhu, Mazhar Memon, Frank L. Berry +2 more | 2014-02-04 |
| 8307105 | Message communication techniques | Steven R. King, Xia Zhu, Mazhar Memon, Frank L. Berry, Nitin Bhardwaj +2 more | 2012-11-06 |
| 8041854 | Steering data units to a consumer | Anil Vasudevan, Partha Sarangam, Sujoy Sen | 2011-10-18 |
| 7996548 | Message communication techniques | Steven R. King, Xia Zhu, Mazhar Memon, Frank L. Berry, Nitin Bhardwaj +2 more | 2011-08-09 |
| 7512750 | Processor and memory controller capable of use in computing system that employs compressed cache lines' worth of information | Chris J. Newburn, Herbert Hum, Ali-Reza Adl-Tabatabai, Anwar Ghuloum | 2009-03-31 |
| 7502877 | Dynamically setting routing information to transfer input output data directly into processor caches in a multi processor system | Raymond S. Tetrick | 2009-03-10 |
| 7257693 | Multi-processor computing system that employs compressed cache lines' worth of information and processor capable of use in said system | Chris J. Newburn, Herbert Hum, Ali-Reza Adl-Tabatabai, Anwar Ghuloum | 2007-08-14 |
| 7231470 | Dynamically setting routing information to transfer input output data directly into processor caches in a multi processor system | Raymond S. Tetrick | 2007-06-12 |
| 7185147 | Striping across multiple cache lines to prevent false sharing | Ramesh Illikkal | 2007-02-27 |
| 7143238 | Mechanism to compress data in a cache | Ali-Reza Adl-Tabatabai, Anwar Ghuloum, Chris J. Newburn | 2006-11-28 |
| 6785793 | Method and apparatus for memory access scheduling to reduce memory access latency | Nagi Aboulenein, Randy B. Osborne, Vamsee K. Madavarapu, Ken M. Crocker | 2004-08-31 |