Issued Patents All Time
Showing 1–24 of 24 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12058044 | Apparatus and method of routing a request in a mesh network | — | 2024-08-06 |
| 11042297 | Techniques to configure a solid state drive to operate in a storage mode or a memory mode | Blaise Fanning, Mark A. Schmisseur, Robert J. Royer, Jr., David B. Minturn, Shane Matthews | 2021-06-22 |
| 10817201 | Multi-level memory with direct access | Blaise Fanning, Shekoufeh Qawami, Frank T. Hady | 2020-10-27 |
| 10296217 | Techniques to configure a solid state drive to operate in a storage mode or a memory mode | Blaise Fanning, Mark A. Schmisseur, Robert J. Royer, Jr., David B. Minturn, Shane Matthews | 2019-05-21 |
| 10241710 | Multi-level memory with direct access | Blaise Fanning, Shekoufeh Qawami, Frank T. Hady | 2019-03-26 |
| 9703502 | Multi-level memory with direct access | Blaise Fanning, Shekoufeh Qawami, Frank T. Hady | 2017-07-11 |
| 9678666 | Techniques to configure a solid state drive to operate in a storage mode or a memory mode | Blaise Fanning, Mark A. Schmisseur, Robert J. Royer, Jr., David B. Minturn, Shane Matthews | 2017-06-13 |
| 9430151 | Multi-level memory with direct access | Blaise Fanning, Shekoufeh Qawami, Frank T. Hady | 2016-08-30 |
| 9190124 | Multi-level memory with direct access | Blaise Fanning, Shekoufeh Qawami, Frank T. Hady | 2015-11-17 |
| 9098402 | Techniques to configure a solid state drive to operate in a storage mode or a memory mode | Blaise Fanning, Mark A. Schmisseur, Robert J. Royer, Jr., David B. Minturn, Shane Matthews | 2015-08-04 |
| 8386701 | Apparatus and method for multi-level cache utilization | Dale Juenemann, Robert Brennan | 2013-02-26 |
| 7783809 | Virtualization of pin functionality in a point-to-point interface | Keshavan Tiruvallur, David I. Poisner, Herbert Hum, Frank Binns, David L. Hill +1 more | 2010-08-24 |
| 7502877 | Dynamically setting routing information to transfer input output data directly into processor caches in a multi processor system | Ram Huggahalli | 2009-03-10 |
| 7360027 | Method and apparatus for initiating CPU data prefetches by an external agent | Ramakrishna Huggahalli, Brannon Batson, Robert G. Blankenship | 2008-04-15 |
| 7231470 | Dynamically setting routing information to transfer input output data directly into processor caches in a multi processor system | Ram Huggahalli | 2007-06-12 |
| 7089399 | Adaptive prefetch of I/O data blocks | — | 2006-08-08 |
| 6912556 | Silicon averaging measurement circuit | — | 2005-06-28 |
| 6757798 | Method and apparatus for arbitrating deferred read requests | — | 2004-06-29 |
| 6622212 | Adaptive prefetch of I/O data blocks | — | 2003-09-16 |
| 6598199 | Memory array organization | — | 2003-07-22 |
| 6006301 | Multi-delivery scheme interrupt router | — | 1999-12-21 |
| 6003112 | Memory controller and method for clearing or copying memory utilizing register files to store address information | — | 1999-12-14 |
| 4807109 | High speed synchronous/asynchronous local bus and data transfer method | Robert L. Farrell, Alireza Sarabi | 1989-02-21 |
| 4570220 | High speed parallel bus and data transfer method | John Beaston, Robert L. Farrell, Alireza Sarabi, Sudarshan Balachandran, Edwin L. Jacks, Jr. +1 more | 1986-02-11 |