Issued Patents All Time
Showing 25 most recent of 49 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12061550 | Coherent multiprocessing enabled compute in storage and memory | Sanjeev N. Trika | 2024-08-13 |
| 11789880 | Load reduced nonvolatile memory interface | Emily Po-Kay Chung, George Vergis | 2023-10-17 |
| 11500795 | Load reduced nonvolatile memory interface | Emily Po-Kay Chung, George Vergis | 2022-11-15 |
| 11016895 | Caching for heterogeneous processors | Mason Cabot, Mark Rosenbluth, John Beck | 2021-05-25 |
| 10817201 | Multi-level memory with direct access | Blaise Fanning, Shekoufeh Qawami, Raymond S. Tetrick | 2020-10-27 |
| 10459855 | Load reduced nonvolatile memory interface | Emily Po-Kay Chung, George Vergis | 2019-10-29 |
| 10339061 | Caching for heterogeneous processors | Mason Cabot, Mark Rosenbluth, John Beck | 2019-07-02 |
| 10318185 | Method and apparatus to provide both storage mode and memory mode access to non-volatile memory within a solid state drive | — | 2019-06-11 |
| 10241710 | Multi-level memory with direct access | Blaise Fanning, Shekoufeh Qawami, Raymond S. Tetrick | 2019-03-26 |
| 10153015 | Managing disturbance induced errors | Prashant S. Damle, Paul D. Ruby, Kiran Pangal, Sowmiya Jayachandran | 2018-12-11 |
| 10089270 | Interchangeable power and signal contacts for IO connectors | Stephen R. Mooney, Howard L. Heck, James E. Jaussi, Bryan K. Casper | 2018-10-02 |
| 10031845 | Method and apparatus for processing sequential writes to a block group of physical blocks in a memory device | — | 2018-07-24 |
| 10019198 | Method and apparatus for processing sequential writes to portions of an addressable unit | — | 2018-07-10 |
| 9965393 | Caching for heterogeneous processors | Mason Cabot, Mark Rosenbluth, John Beck | 2018-05-08 |
| 9804646 | Host controlled IO power management | James E. Jaussi, Stephen R. Mooney, Howard L. Heck, Bryan K. Casper | 2017-10-31 |
| 9792963 | Managing disturbance induced errors | Prashant S. Damle, Paul D. Ruby, Kiran Pangal, Sowmiya Jayachandran | 2017-10-17 |
| 9703502 | Multi-level memory with direct access | Blaise Fanning, Shekoufeh Qawami, Raymond S. Tetrick | 2017-07-11 |
| 9430151 | Multi-level memory with direct access | Blaise Fanning, Shekoufeh Qawami, Raymond S. Tetrick | 2016-08-30 |
| 9312908 | Universal IO connector and interface capable of both wired and wireless operation | Stephen R. Mooney, Howard L. Heck, James E. Jaussi, Bryan K. Casper, Debabani Choudhury | 2016-04-12 |
| 9235550 | Caching for heterogeneous processors | Mason Cabot, John Beck, Mark Rosenbluth | 2016-01-12 |
| 9202547 | Managing disturbance induced errors | Prashant S. Damle, Paul D. Ruby, Kiran Pangal, Sowmiya Jayachandran | 2015-12-01 |
| 9190124 | Multi-level memory with direct access | Blaise Fanning, Shekoufeh Qawami, Raymond S. Tetrick | 2015-11-17 |
| 9152432 | System and method to accelerate access to network data using a networking unit accessible non-volatile storage | Mason Cabot | 2015-10-06 |
| 8934505 | Synchronizing multiple system clocks | Kevin B. Stanton | 2015-01-13 |
| 8799579 | Caching for heterogeneous processors | Mason Cabot, John Beck, Mark Rosenbluth | 2014-08-05 |