SJ

Sowmiya Jayachandran

IN Intel: 8 patents #4,870 of 30,777Top 20%
Micron: 3 patents #3,077 of 6,345Top 50%
Overall (All Time): #449,925 of 4,157,543Top 15%
11
Patents All Time

Issued Patents All Time

Patent #TitleCo-InventorsDate
11249531 Apparatuses and methods for exiting low power states in memory devices Rajesh Sundaram, William Low 2022-02-15
11036412 Dynamically changing between latency-focused read operation and bandwidth-focused read operation Sahar Khalili, Zvika Greenfield, Robert J. Royer, Jr., Dimpesh Patel 2021-06-15
10437307 Apparatuses and methods for exiting low power states in memory devices Rajesh Sundaram, William Low 2019-10-08
10153015 Managing disturbance induced errors Prashant S. Damle, Frank T. Hady, Paul D. Ruby, Kiran Pangal 2018-12-11
9916104 Techniques for entry to a lower power state for a memory device Rajesh Sundaram, Robert W. Faber 2018-03-13
9818458 Techniques for entry to a lower power state for a memory device Rajesh Sundaram, Robert W. Faber 2017-11-14
9792963 Managing disturbance induced errors Prashant S. Damle, Frank T. Hady, Paul D. Ruby, Kiran Pangal 2017-10-17
9778723 Apparatuses and methods for exiting low power states in memory devices Rajesh Sundaram, William Low 2017-10-03
9417684 Mechanism for facilitating power and performance management of non-volatile memory in computing devices Simon Ramage, Jason A. Gayman, Joerg Hartung, Curtis A. Gittens, Richard P. Mangold 2016-08-16
9202547 Managing disturbance induced errors Prashant S. Damle, Frank T. Hady, Paul D. Ruby, Kiran Pangal 2015-12-01
8001444 ECC functional block placement in a multi-channel mass storage device Andrew W. Vogan, Jawad B. Khan 2011-08-16