Issued Patents All Time
Showing 1–7 of 7 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11188467 | Multi-level system memory with near memory capable of storing compressed cache lines | Israel Diamand, Alaa R. Alameldeen, Sreenivas Subramoney, Srinivas Santosh Kumar MADUGULA, Jayesh Gaur +2 more | 2021-11-30 |
| 10635593 | Create page locality in cache controller cache allocation | Daniel Greenspan, Anant Vithal Nori, Yoav Lossin, Asaf Rubinstein | 2020-04-28 |
| 10176099 | Using data pattern to mark cache lines as invalid | Jayesh Gaur, Zvika Greenfield, Israel Diamand | 2019-01-08 |
| 9846648 | Create page locality in cache controller cache allocation | Daniel Greenspan, Anant Vithal Nori, Yoav Lossin, Asaf Rubinstein | 2017-12-19 |
| 9542325 | Adjustable over-restrictive cache locking limit for improved overall performance | Daniel Greenspan | 2017-01-10 |
| 9424620 | Identification of GPU phase to determine GPU scalability during runtime | Idan Mondjak, Eyal Yaacoby | 2016-08-23 |
| 9396120 | Adjustable over-restrictive cache locking limit for improved overall performance | Daniel Greenspan | 2016-07-19 |