Issued Patents All Time
Showing 1–22 of 22 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12165686 | Memory power management method and apparatus | Nivedha Krishnakumar, Virendra Vikramsinh Adsure, Jaya L. Jeyaseelan, Barnes Cooper, Toby Opferman +2 more | 2024-12-10 |
| 11687681 | Multi-tenant cryptographic memory isolation | Shay Gueron, Siddhartha Chhabra | 2023-06-27 |
| 11520498 | Memory management to improve power performance | Sridhar Muthrasanallur, Srinivas Pandruvada, Vishwanath Somayaji, Prashant Kodali | 2022-12-06 |
| 10877693 | Architecture for dynamic transformation of memory configuration | Julius Mandelblat, Nir Sucher | 2020-12-29 |
| 10802567 | Performing local power gating in a processor | Ron Gabor, Zeev Sperber, Vjekoslav Svilan, David N. Mackintosh, Jose A. Baiocchi Paredes +2 more | 2020-10-13 |
| 10776525 | Multi-tenant cryptographic memory isolation | Shay Gueron, Siddhartha Chhabra | 2020-09-15 |
| 10680613 | Programmable on-die termination timing in a multi-rank system | Kuljit S. Bains, Alexey Kostinsky | 2020-06-09 |
| 10558570 | Concurrent accesses of asymmetrical memory sources | Zvika Greenfield, Randy B. Osborne | 2020-02-11 |
| 10141935 | Programmable on-die termination timing in a multi-rank system | Kuljit S. Bains, Alexey Kostinsky | 2018-11-27 |
| 10109340 | Precharging and refreshing banks in memory device with bank group architecture | Kuljit S. Bains, John B. Halbert, Tomer Levy | 2018-10-23 |
| 10055346 | Polarity based data transfer function for volatile memory | — | 2018-08-21 |
| 9948299 | On-die termination control without a dedicated pin in a multi-rank system | Kuljit S. Bains, Christopher E. Cox, Alexey Kostinsky | 2018-04-17 |
| 9871519 | On-die termination control without a dedicated pin in a multi-rank system | Kuljit S. Bains, Christopher E. Cox, Alexey Kostinsky | 2018-01-16 |
| 9780782 | On-die termination control without a dedicated pin in a multi-rank system | Kuljit S. Bains | 2017-10-03 |
| 9772674 | Performing local power gating in a processor | Ron Gabor, Zeev Sperber, Vjekoslav Svilan, David N. Mackintosh, Jose A. Baiocchi Paredes +2 more | 2017-09-26 |
| 9740610 | Polarity based data transfer function for volatile memory | — | 2017-08-22 |
| 9728245 | Precharging and refreshing banks in memory device with bank group architecture | Kuljit S. Bains, John B. Halbert, Tomer Levy | 2017-08-08 |
| 9640277 | Avoiding DQS false sampling triggers | Alexey Kostinsky | 2017-05-02 |
| 9582430 | Asymmetric set combined cache | Zvika Greenfield, Israel Diamand | 2017-02-28 |
| 9558066 | Exchanging ECC metadata between memory and host system | Kuljit S. Bains, John B. Halbert | 2017-01-31 |
| 9229524 | Performing local power gating in a processor | Ron Gabor, Zeev Sperber, Vjekoslav Svilan, David N. Mackintosh, Jose Angel Paredes +2 more | 2016-01-05 |
| 8959266 | Dynamic priority control based on latency tolerance | Todd M. Witter, Eran Shifer, Tomer Levy, Zvika Greenfield, Anant Vithal Nori | 2015-02-17 |