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USPTO Patent Rankings Data through Dec 31, 2025
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Chih-Cheh Chen — 9 Patents

Intel: 7 patents #5,443 of 30,777Top 20%
NENetlist: 2 patents #21 of 30Top 70%
Hillsboro, OR: #486 of 2,365 inventorsTop 25%
Oregon: #4,727 of 28,073 inventorsTop 20%
Overall (All Time): #535,341 of 4,157,543Top 15%
9 Patents All Time
Chih-Cheh Chen has been granted 9 US patents while listed as an inventor at Intel. The first was granted in 2000 and the most recent in August 2024. Chih-Cheh Chen ranks #535,341 of 4,157,543 US inventors in our database (top 12.9%). Patent records list Chih-Cheh Chen in Hillsboro, OR, US.

Issued Patents All Time

Showing 1–9 of 9 patents

Patent #TitleCo-InventorsDateApprox Value ⓘ
12061562 Computer memory expansion device and method of operation Jordan Horwich, Jerry Alston, Patrick S. Lee, Scott H. Milton, Jeekyoung Park 2024-08-13
11500797 Computer memory expansion device and method of operation Jordan Horwich, Jerry Alston, Patrick S. Lee, Scott H. Milton, Jeekyoung Park 2022-11-15
10929330 External resource discovery and coordination in a data center Russell J. Wunderlich, Tina C. Zhong 2021-02-23 $31,062,000
10817454 Dynamic lane access switching between PCIe root spaces Janusz Jurski, Amit Kumar Srivastava, Malay Trivedi, James Mitchell, Piotr Kwidzinski +1 more 2020-10-27 $34,955,000
10620966 Method to coordinate system boot and reset flows and improve reliability, availability and serviceability (RAS) among multiple chipsets Tina C. Zhong, Russell J. Wunderlich, Malay Trivedi 2020-04-14 $33,667,000
8908688 Multicast support on a switch for PCIe endpoint devices Michael T. Klinglesmith, David M. Lee, John Zulauf, Itay Franko, Peter J. Elardo +2 more 2014-12-09 $17,877,000
8270405 Multicast support on a switch for PCIe endpoint devices Michael T. Klinglesmith, David M. Lee, John Zulauf, Itay Franko, Peter J. Elardo +2 more 2012-09-18 $22,462,000
6298420 Coherent variable length reads from system memory Suresh Chittor, Sin S. Tan, Jonathan Spitz 2001-10-02 $98,303,000
6061764 Coherent variable length reads which implicates multiple cache lines by a memory controller connected to a serial and a pipelined bus utilizing a plurality of atomic transactions Suresh Chittor, Sin S. Tan, Jonathan Spitz 2000-05-09 $498,077,000