Issued Patents All Time
Showing 51–72 of 72 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9213491 | Disabling a command associated with a memory device | Kuljit S. Bains | 2015-12-15 |
| 9196384 | Memory subsystem performance based on in-system weak bit detection | Theodore Z. Schoenborn | 2015-11-24 |
| 9117544 | Row hammer refresh command | Kuljit S. Bains, John B. Halbert, Theodore Z. Schoenborn, Zvika Greenfield | 2015-08-25 |
| 9076499 | Refresh rate performance based on in-system weak bit detection | Theodore Z. Schoenborn | 2015-07-07 |
| 9026725 | Training for command/address/control/clock delays under uncertain initial conditions and for mapping swizzled data to command/address signals | Alexey Kostinsky, Zvika Greenfield, Pavel Konev, Olga Fomenko | 2015-05-05 |
| 9009531 | Memory subsystem data bus stress testing | Theodore Z. Schoenborn, James M. Shehadi, David G. Ellis | 2015-04-14 |
| 9009540 | Memory subsystem command bus stress testing | Theodore Z. Schoenborn, James M. Shehadi, David G. Ellis, Tomer Levy, Zvika Greenfield | 2015-04-14 |
| 9003246 | Functional memory array testing with a transaction-level test engine | Theodore Z. Schoenborn, James M. Shehadi | 2015-04-07 |
| 8996934 | Transaction-level testing of memory I/O and memory device | Theodore Z. Schoenborn, James M. Shehadi | 2015-03-31 |
| 8938573 | Row hammer condition monitoring | Zvika Greenfield, Kuljit S. Bains, Theodore Z. Schoenborn, John B. Halbert | 2015-01-20 |
| 8929157 | Power efficient, single-ended termination using on-die voltage supply | Navindra Navaratnam, Mahmoud Elassal | 2015-01-06 |
| 8868992 | Robust memory link testing using memory controller | Bryan L. Spry, Theodore Z. Schoenborn, Philip Abraham, David G. Ellis, Jay Nejedlo +6 more | 2014-10-21 |
| 8819474 | Active training of memory command timing | Theodore Z. Schoenborn, John V. Lovelace, Bryan L. Spry | 2014-08-26 |
| 8762607 | Mechanism for facilitating dynamic multi-mode memory packages in memory systems | Christopher E. Cox, Rebecca Z. Loop | 2014-06-24 |
| 8582374 | Method and apparatus for dynamically adjusting voltage reference to optimize an I/O system | Kevin B. Moore, John V. Lovelace, Zale Schoenborn, Bryan L. Spry, Chris Yunker | 2013-11-12 |
| 8514533 | Method, apparatus, and system for protecting supply nodes from electrostatic discharge | Victor Zia | 2013-08-20 |
| 8503678 | Suppressing power supply noise using data scrambling in double data rate memory systems | Maynard C. Falconer, Adam Norman | 2013-08-06 |
| 8331176 | Method and system for evaluating effects of signal phase difference on a memory system | Kevin B. Moore, John V. Lovelace, Zale Schoenborn, Bryan L. Spry, Christopher E. Yunker | 2012-12-11 |
| 8248124 | Methods and apparatuses for delay-locked loops and phase-locked loops | Praveen Mosalikanti, Nasser A. Kurd | 2012-08-21 |
| 7945050 | Suppressing power supply noise using data scrambling in double data rate memory systems | — | 2011-05-17 |
| 7886174 | Memory link training | Bryan L. Spry, Stanley S. Kulick | 2011-02-08 |
| 7647476 | Common analog interface for multiple processor cores | Jeffrey D. Gilbert, Ganapati Srinivasa | 2010-01-12 |