Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › DDR memory bus with a reduced data strobe signal preamble timespan

DDR memory bus with a reduced data strobe signal preamble timespan

US Patent 10541018 · Granted Jan 21, 2020

Estimated economic value: $31,546,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Techniques for command bus training to a memory device2025
Memory device package with noise shielding2025
Distribution of error checking and correction (ECC) bits to allocate ECC bits fo2025
Techniques for duty cycle correction2025
Stacked memory chip solution with reduced package inputs/outputs (I/Os)2025
Buffer that supports burst transfers having parallel CRC and data transmissions2025
Fast self-refresh exit power state2025
Reading from a mode register having different read and write timing2025
Machine learning techniques for extracting floorplan elements from architectural2025
Apparatus and method to increase effective capacitance with layout staples2025
Apparatus, system and method to detect and improve an input clock performance of2025
Building datum extraction from laser scanning data2024