Issued Patents All Time
Showing 51–75 of 99 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9030903 | Method, apparatus and system for providing a memory refresh | Kuljit S. Bains, Suneeta Sah, Zvika Greenfield | 2015-05-12 |
| 8971087 | Stacked memory with interface providing offset interconnects | Pete D. Vogt, Andre Schaefer, Warren R. Morrow, Jin-Sung Kim, Kenneth D. Shoemaker | 2015-03-03 |
| 8938573 | Row hammer condition monitoring | Zvika Greenfield, Kuljit S. Bains, Theodore Z. Schoenborn, Christopher P. Mozak | 2015-01-20 |
| 8862973 | Method and system for error management in a memory device | Kuljit S. Bains, David J. Zimmerman, Dennis W. Brzezinski, Michael W. Williams | 2014-10-14 |
| 8811110 | Configuration for power reduction in DRAM | Andre Schaefer | 2014-08-19 |
| 8385146 | Memory throughput increase via fine granularity of precharge management | Kuljit S. Bains | 2013-02-26 |
| 8289797 | Method, apparatus, and system for active refresh management | Sandeep Jain, Animesh Mishra | 2012-10-16 |
| 8238189 | Common memory device for variable device width and scalable pre-fetch and page size | Kuljit S. Bains | 2012-08-07 |
| 8161356 | Systems, methods, and apparatuses to save memory self-refresh power | Kuljit S. Bains, Michael W. Williams | 2012-04-17 |
| 8130576 | Memory throughput increase via fine granularity of precharge management | Kuljit S. Bains | 2012-03-06 |
| 7957216 | Common memory device for variable device width and scalable pre-fetch and page size | Kuljit S. Bains | 2011-06-07 |
| 7523230 | Device and method for maximizing performance on a memory interface with a variable number of channels | James M. Dodd, Brian P. Johnson, Jay C. Wells | 2009-04-21 |
| 7450456 | Temperature determination and communication for multiple devices of a memory module | Sandeep Jain, David Wyatt, Jun Shi, Animesh Mishra, Melik Isbara | 2008-11-11 |
| 7412627 | Method and apparatus for providing debug functionality in a buffered memory channel | Kuljit S. Bains, Robert M. Ellis, Chris Freeman, David J. Zimmerman | 2008-08-12 |
| 7404055 | Memory transfer with early access to critical portion | Kuljit S. Bains, Greg Lemos, Randy B. Osborne | 2008-07-22 |
| 7386765 | Memory device having error checking and correction | Robert M. Ellis, Kuljit S. Bains, Chris Freeman | 2008-06-10 |
| 7353329 | Memory buffer device integrating refresh logic | Robert M. Ellis, Kuljit S. Bains, Chris Freeman, Narendra S. Khandekar, Michael W. Williams | 2008-04-01 |
| 7349233 | Memory device with read data from different banks | Kuljit S. Bains | 2008-03-25 |
| 7350016 | High speed DRAM cache architecture | Kuljit S. Bains, Herbert Hum | 2008-03-25 |
| 7342841 | Method, apparatus, and system for active refresh management | Sandeep Jain, Animesh Mishra | 2008-03-11 |
| 7281079 | Method and apparatus to counter mismatched burst lengths | Kuljit S. Bains, Randy B. Osborne | 2007-10-09 |
| 7260007 | Temperature determination and communication for multiple devices of a memory module | Sandeep Jain, David Wyatt, Jun Shi, Animesh Mishra, Melik Isbara | 2007-08-21 |
| 7249232 | Buffering and interleaving data transfer between a chipset and memory modules | Jim M. Dodd, Chung Lam, Randy M. Bonella | 2007-07-24 |
| 7243205 | Buffered memory module with implicit to explicit memory command expansion | Chris Freeman, Pete D. Vogt, Kuljit S. Bains, Robert M. Ellis, Michael W. Williams | 2007-07-10 |
| 7054999 | High speed DRAM cache architecture | Kuljit S. Bains, Herbert Hum | 2006-05-30 |