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Memory buffer device integrating refresh logic |
Robert M. Ellis, Kuljit S. Bains, Chris Freeman, John B. Halbert, Michael W. Williams |
2008-04-01 |
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Method and apparatus for controlling power states in a memory device utilizing state information |
James M. Dodd |
2006-02-14 |
| 6981089 |
Memory bus termination with memory unit having termination control |
James M. Dodd |
2005-12-27 |
| 6976121 |
Apparatus and method to track command signal occurrence for DRAM data transfer |
Michael W. Williams, Howard S. David |
2005-12-13 |
| 6976120 |
Apparatus and method to track flag transitions for DRAM data transfer |
Michael W. Williams, Howard S. David |
2005-12-13 |
| 6832177 |
Method of addressing individual memory devices on a memory module |
Howard S. David |
2004-12-14 |
| 6829184 |
Apparatus and method for encoding auto-precharge |
Michael W. Williams |
2004-12-07 |
| 6639820 |
Memory buffer arrangement |
James M. Dodd |
2003-10-28 |
| 6567904 |
Method and apparatus for automatically detecting whether a memory unit location is unpopulated or populated with synchronous or asynchronous memory devices |
Aniruddha Kundu |
2003-05-20 |
| 6502150 |
Method and apparatus for resource sharing in a multi-processor system |
Zohar Bogin, Steve John Clohset |
2002-12-31 |
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Speculative request pointer advance for fast back-to-back reads |
David D. Lent, Zohar Bogin |
2002-05-07 |
| 6314497 |
Apparatus and method for maintaining cache coherency in a memory system |
Steve John Clohset, Zohar Bogin |
2001-11-06 |
| 6243768 |
Method and apparatus for controlling data transfer between a synchronous DRAM-type memory and a system bus |
— |
2001-06-05 |
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Arbitration methods to avoid deadlock and livelock when performing transactions across a bridge |
Ashish S. Gadagkar, Zohar Bogin, David D. Lent |
2001-03-13 |
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Method and apparatus for decoupling internal latencies of a bus bridge from those on an external bus |
Zohar Bogin, Steve John Clohset |
2001-01-09 |
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AGP read and CPU wire coherency |
Zohar Bogin, Vincent E. VonBokern |
2000-12-05 |
| 6154825 |
Method and apparatus for addressing a memory resource comprising memory devices having multiple configurations |
Robert N. Murdoch, Michael W. Williams, Kuljit S. Bains |
2000-11-28 |
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Method and apparatus for controlling data transfer between a synchronous DRAM-type memory and a system bus |
— |
1999-07-20 |
| 5873119 |
Method for parallel processing of dram read request in a memory-cache controller system |
Vincent Edward Von Bokern |
1999-02-16 |
| 5802603 |
Method and apparatus for asymmetric/symmetric DRAM detection |
Kuljit S. Bains |
1998-09-01 |
| 5715476 |
Method and apparatus for controlling linear and toggle mode burst access sequences using toggle mode increment logic |
Aniruddha Kundu |
1998-02-03 |