Robert N. Murdoch — 15 Patents at Intel

Robert N. Murdoch has been granted 15 US patents while listed as an inventor at Intel. The first was granted in 1988 and the most recent in April 2002. Robert N. Murdoch ranks #307,048 of 4,157,543 US inventors in our database (top 7.4%). Patent records list Robert N. Murdoch in Sacramento, CA, US.

Issued Patents All Time

Showing 1–15 of 15 patents

Patent #	Title	Co-Inventors	Date	Approx Value ⓘ
6370624	Configurable page closing method and apparatus for multi-port host bridges	Jasmin Ajanovic, Michael W. Williams	2002-04-09	$80,316,000
6226730	Achieving page hit memory cycles on a virtual address reference	Michael W. Williams	2001-05-01	$311,645,000
6199145	Configurable page closing method and apparatus for multi-port host bridges	Jasmin Ajanovic, Michael W. Williams	2001-03-06	$156,843,000
6199151	Apparatus and method for storing a device row indicator for use in a subsequent page-miss memory cycle	Michael W. Williams, Mikal C. Hunsaker	2001-03-06	$156,843,000
6154825	Method and apparatus for addressing a memory resource comprising memory devices having multiple configurations	Michael W. Williams, Kuljit S. Bains, Narendra S. Khandekar	2000-11-28	$170,940,000
5894567	Mechanism for enabling multi-bit counter values to reliably cross between clocking domains	James M. Dodd	1999-04-13	$127,378,000
5889974	Method and apparatus for the detection of reordering hazards	David J. Harriman	1999-03-30	$45,277,000
5860128	Method and apparatus for sampling data from a memory	Michael W. Williams, Sathyamurthi Sadhasivan	1999-01-12	$79,273,000
5857082	Method and apparatus for quickly transferring data from a first bus to a second bus	Bruce A. Young, Tony Tarango, David J. Harriman	1999-01-05	$155,215,000
5761444	Method and apparatus for dynamically deferring transactions	Jasmin Ajanovic, Timothy M. Dobbins, Aditya Sreenivas, Stuart E. Sailer, Jeffrey L. Rabe	1998-06-02	$54,938,000
5572692	Memory configuration decoding system having automatic row base address generation mechanism for variable memory devices with row access interleaving	Mohammad Khan	1996-11-05	$57,895,000
5276858	Memory controller with integrated delay line circuitry	Jayawant V. Oak, Craig S. Walker, Thomas F. Heil, Erez Carmel	1994-01-04	$47,323,000
4901235	Data processing system having unique multilevel microcode architecture	Chandra Vora, Donald C. Wiser, Mark B. Hecker	1990-02-13	$1,071,000
4858180	Content addressable memory and self-blocking driver	—	1989-08-15	$3,076,000
4718034	Carry-save propagate adder	Nabil Takla, Mark B. Hecker, Raymond M. Chu, Rajesh Parekh	1988-01-05	$6,973,000

Robert N. Murdoch — 15 Patents

Issued Patents All Time

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