Issued Patents All Time
Showing 76–99 of 99 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7050351 | Method and apparatus for multiple row caches per bank | Robert M. Ellis, Kuljit S. Bains, Chris Freeman | 2006-05-23 |
| 7024518 | Dual-port buffer-to-memory interface | James M. Dodd, Chung Lam, Randy M. Bonella, Thomas J. Holman | 2006-04-04 |
| 6996749 | Method and apparatus for providing debug functionality in a buffered memory channel | Kuljit S. Bains, Robert M. Ellis, Chris Freeman, David J. Zimmerman | 2006-02-07 |
| 6990036 | Method and apparatus for multiple row caches per bank | Robert M. Ellis, Kuljit S. Bains, Chris Freeman | 2006-01-24 |
| 6954822 | Techniques to map cache data to memory arrays | Kuljit S. Bains, Herbert Hum | 2005-10-11 |
| 6952745 | Device and method for maximizing performance on a memory interface with a variable number of channels | James M. Dodd, Brian P. Johnson, Jay C. Wells | 2005-10-04 |
| 6928593 | Memory module and memory component built-in self test | Randy M. Bonella | 2005-08-09 |
| 6928571 | Digital system of adjusting delays on circuit boards | Randy M. Bonella | 2005-08-09 |
| 6820163 | Buffering data transfer between a chipset and memory modules | James A. McCall, Randy M. Bonella, Jim M. Dodd, Chung Lam | 2004-11-16 |
| 6785190 | Method for opening pages of memory with a single command | Kuljit S. Bains | 2004-08-31 |
| 6766385 | Device and method for maximizing performance on a memory interface with a variable number of channels | James M. Dodd, Brian P. Johnson, Jay C. Wells | 2004-07-20 |
| 6747887 | Memory module having buffer for isolating stacked memory devices | Randy M. Bonella | 2004-06-08 |
| 6742098 | Dual-port buffer-to-memory interface | James M. Dodd, Chung Lam, Randy M. Bonella | 2004-05-25 |
| 6697888 | Buffering and interleaving data transfer between a chipset and memory modules | Jim M. Dodd, Chung Lam, Randy M. Bonella | 2004-02-24 |
| 6658509 | Multi-tier point-to-point ring memory interface | Randy M. Bonella | 2003-12-02 |
| 6625687 | Memory module employing a junction circuit for point-to-point connection isolation, voltage translation, data synchronization, and multiplexing/demultiplexing | Jim M. Dodd, Chung Lam, Randy M. Bonella | 2003-09-23 |
| 6553450 | Buffer to multiply memory interface | Jim M. Dodd, Michael W. Williams, Randy M. Bonella, Chung Lam | 2003-04-22 |
| 6530006 | System and method for providing reliable transmission in a buffered memory system | James M. Dodd, Michael W. Williams, Randy M. Bonella | 2003-03-04 |
| 6493250 | Multi-tier point-to-point buffered memory interface | James M. Dodd, Chung Lam, Randy M. Bonella | 2002-12-10 |
| 6487102 | Memory module having buffer for isolating stacked memory devices | Randy M. Bonella | 2002-11-26 |
| 6449213 | Memory interface having source-synchronous command/address signaling | James M. Dodd, Michael W. Williams, Randy M. Bonella | 2002-09-10 |
| 6369605 | Self-terminated driver to prevent signal reflections of transmissions between electronic devices | Randy M. Bonella | 2002-04-09 |
| 6317352 | Apparatus for implementing a buffered daisy chain connection between a memory controller and memory modules | Jim M. Dodd, Chung Lam, Randy M. Bonella | 2001-11-13 |
| 4985872 | Sequencing column select circuit for a random access memory | — | 1991-01-15 |