| 7249232 |
Buffering and interleaving data transfer between a chipset and memory modules |
John B. Halbert, Chung Lam, Randy M. Bonella |
2007-07-24 |
| 6820163 |
Buffering data transfer between a chipset and memory modules |
James A. McCall, Randy M. Bonella, John B. Halbert, Chung Lam |
2004-11-16 |
| 6804764 |
Write clock and data window tuning based on rank select |
Paul A. LaBerge |
2004-10-12 |
| 6697888 |
Buffering and interleaving data transfer between a chipset and memory modules |
John B. Halbert, Chung Lam, Randy M. Bonella |
2004-02-24 |
| 6625687 |
Memory module employing a junction circuit for point-to-point connection isolation, voltage translation, data synchronization, and multiplexing/demultiplexing |
John B. Halbert, Chung Lam, Randy M. Bonella |
2003-09-23 |
| 6553450 |
Buffer to multiply memory interface |
Michael W. Williams, John B. Halbert, Randy M. Bonella, Chung Lam |
2003-04-22 |
| 6400631 |
Circuit, system and method for executing a refresh in an active memory bank |
Michael W. Williams |
2002-06-04 |
| 6317352 |
Apparatus for implementing a buffered daisy chain connection between a memory controller and memory modules |
John B. Halbert, Chung Lam, Randy M. Bonella |
2001-11-13 |