Issued Patents All Time
Showing 25 most recent of 32 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11915745 | Low standby leakage implementation for static random access memory | Mayank Tayal, Sagar V. Reddy | 2024-02-27 |
| 11017858 | Low power content addressable memory | — | 2021-05-25 |
| 7685451 | Method and apparatus to limit current-change induced voltage changes in a microcircuit | James S. Burns, Kenneth D. Shoemaker, Tom E. Wang, David J. Ayers, Vivek Tiwari | 2010-03-23 |
| 6952118 | Gate-clocked domino circuits with reduced leakage current | Shahram Jamshidi | 2005-10-04 |
| 6833735 | Single stage pulsed domino circuit for driving cascaded skewed static logic circuits | Jiann-Cherng Lan, Snehal T Jariwala, Wenjie Jiang | 2004-12-21 |
| 6820106 | Method and apparatus for improving the performance of a floating point multiplier accumulator | Narsing Vijayrao, Chi Keung Lee | 2004-11-16 |
| 6707318 | Low power entry latch to interface static logic with dynamic logic | Shahram Jamshidi | 2004-03-16 |
| 6631093 | Low power precharge scheme for memory bit lines | Jiann-Cherng Lan, Wenjie Jiang, Gaurav Mehta, Sadhana Madhyastha | 2003-10-07 |
| 6628539 | Multi-entry register cell | Gaurav Mehta, Sadhana Madhyastha, Jiann-Cherng Lan | 2003-09-30 |
| 6629194 | Method and apparatus for low power memory bit line precharge | Gaurav Mehta, Sadhana Madhyastha, Jiann-Cherng Lan | 2003-09-30 |
| 6593776 | Method and apparatus for low power domino decoding | Gaurav Mehta, Vivek Joshi | 2003-07-15 |
| 6369616 | Low power clock buffer with shared, precharge transistor | Jiann-Cherng Lan | 2002-04-09 |
| 6351151 | Method and apparatus for reducing soft errors in dynamic circuits | Wenjie Jiang | 2002-02-26 |
| 6341099 | Reducing power consumption in a data storage device | Sadhana Madhyastha, Gaurav Mehta, Jiann-Cherng Lan | 2002-01-22 |
| 6292029 | Method and apparatus for reducing soft errors in dynamic circuits | Wenjie Jiang | 2001-09-18 |
| 6266757 | High speed four-to-two carry save adder | Mehul Desai | 2001-07-24 |
| 6205463 | Fast 2-input 32-bit domino adder | Rajesh Manglore | 2001-03-20 |
| 6127850 | Low power clock buffer with shared, clocked transistor | Jiann-Cherng Lan | 2000-10-03 |
| 6124737 | Low power clock buffer having a reduced, clocked, pull-down transistor | Jiann-Cherng Lan, Kamal J. Koshy | 2000-09-26 |
| 6111435 | Low power multiplexer with shared, clocked transistor | Jiann-Cherng Lan, Mahadevamurty Nemani, Narsing Vijayrao, Wenjie Jiang | 2000-08-29 |
| 6058403 | Broken stack priority encoder | Narsing Vijayrao | 2000-05-02 |
| 6023767 | Method for verifying hold time in integrated circuit design | James J. D. Lan, Rajesh Manglore | 2000-02-08 |
| 5944777 | Method and apparatus for generating carries in an adder circuit | Sanjay Kumar | 1999-08-31 |
| 5900744 | Method and apparatus for providing a high speed tristate buffer | Bharat K. Bisen | 1999-05-04 |
| 5889693 | CMOS sum select incrementor | Vivek Joshi | 1999-03-30 |