Issued Patents All Time
Showing 25 most recent of 26 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11555837 | Volt-var device monitor | Ashwin Shirsat | 2023-01-17 |
| 11113232 | Disaggregated computer system | Chih-Chieh Chang, Chang GENG | 2021-09-07 |
| 11061056 | Voltage rating validator for advanced metering | Umang Deora | 2021-07-13 |
| 10996247 | Volt-VAR device monitor | Ashwin Shirsat | 2021-05-04 |
| 10972512 | System and method for identifying idle resources in communication endpoints | Abhishek Gupta, Dhananjay Shende | 2021-04-06 |
| 10964362 | Three-port memory cell and array for in-memory computing | Zhewei Jiang, Muhammed Ahosan Ul Karim, Xi Cao, Jack M. Higman | 2021-03-30 |
| 10769850 | Systems and methods for efficient updating of an analysis mesh | Frank E. DeSimone, Joseph Borella, John Svitek, Mukesh Bauskar, James M. West +1 more | 2020-09-08 |
| 10412126 | Detection and auto-correction of talk path problems in communication sessions | Anirudh Patel, Manish H. Patil, Mani Sharma | 2019-09-10 |
| 9900230 | Dissemination of quality of service information in a distributed environment | Anirudh Patel, Manish H. Patil | 2018-02-20 |
| 9781026 | System and method to prevent polling overload for detection of presence information | Dhananjay Shende | 2017-10-03 |
| 9548136 | Method to identify extrinsic SRAM bits for failure analysis based on fail count voltage response | Sriram Balasubramanian, Chad Weintraub, Yoann Mamy Randriamihaja, William F. McMahon | 2017-01-17 |
| 9530488 | Methods, apparatus and system determining dual port DC contention margin | Sriram Balasubramanian, Randy W. Mann, Ratheesh R. Thankalekshmi | 2016-12-27 |
| 8151240 | Effective gate length circuit modeling based on concurrent length and mobility analysis | Kanak B. Agarwal | 2012-04-03 |
| 8136079 | Effective gate length circuit modeling based on concurrent length and mobility analysis | Kanak B. Agarwal | 2012-03-13 |
| 7295564 | Virtual output queue (VoQ) management method and apparatus | Jing Ling, Juan-Carlos Calderon, Jean-Michel Caia, Anguo Huang | 2007-11-13 |
| 7154853 | Rate policing algorithm for packet flows | Jean-Michel Caia, Jing Ling, Juan-Carlos Calderon, Anguo Huang | 2006-12-26 |
| 7065628 | Increasing memory access efficiency for packet applications | Juan-Carlos Calderon, Jing Ling, Jean-Michel Caia, Anguo Huang | 2006-06-20 |
| 7065732 | Method to reduce the power consumption of large PLAs by clock gating guided by recursive shannon decomposition of the and-plane | Victor Konrad | 2006-06-20 |
| 7061867 | Rate-based scheduling for packet applications | Anguo Huang, Jing Ling, Jean-Michel Caia, Juan-Carlos Calderon | 2006-06-13 |
| 6944728 | Interleaving memory access | Juan-Carlos Calderon, Jean-Michel Caia, Jing Ling, Anguo Huang | 2005-09-13 |
| 6892284 | Dynamic memory allocation for assigning partitions to a logical port from two groups of un-assigned partitions based on two threshold values | Jing Ling, Juan-Carlos Calderon, Jean-Michel Caia, Anguo Huang, Steve John Clohset | 2005-05-10 |
| 6593776 | Method and apparatus for low power domino decoding | Sudarshan Kumar, Gaurav Mehta | 2003-07-15 |
| 6564331 | Low power register file | — | 2003-05-13 |
| 6564328 | Microprocessor with digital power throttle | Edward T. Grochowski, Vinod Sharma, Gregory S. Matthews, Ralph M. Kling | 2003-05-13 |
| 6559680 | Data driven keeper for a domino circuit | Bharat Bhushan | 2003-05-06 |