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Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
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Gaurav Mehta — 12 Patents

Intel: 8 patents #4,914 of 30,777Top 20%
ASArtisan Vehicle Systems: 2 patents #7 of 10Top 70%
UCUnited Test And Assembly Center: 1 patents #30 of 65Top 50%
Applied Materials: 1 patents #4,824 of 7,310Top 70%
San Jose, CA: #5,425 of 32,062 inventorsTop 20%
California: #51,404 of 386,348 inventorsTop 15%
Overall (All Time): #396,045 of 4,157,543Top 10%
12 Patents All Time
Gaurav Mehta has been granted 12 US patents while listed as an inventor at Intel. The first was granted in 1998 and the most recent in November 2024. Gaurav Mehta ranks #396,045 of 4,157,543 US inventors in our database (top 9.5%). Patent records list Gaurav Mehta in San Jose, CA, US.

Patents per Year

Patents granted per year, 1998 to 2024Bar chart with a peak of 4 patents in 2003.peak 41998: 1 patents19981999: 2 patents19992002: 1 patents20022003: 4 patents20032010: 1 patents20102022: 1 patents20222023: 1 patents20232024: 1 patents2024

Issued Patents All Time

Showing 1–12 of 12 patents

Patent #TitleCo-InventorsDateApprox Value ⓘ
12139025 Battery assembly stabilization mechanism Kyle Hickey, Nicholas Dickson 2024-11-12
11600492 Electrostatic chuck with reduced current leakage for hybrid laser scribing and plasma etch wafer singulation process Sai Abhinand, Michael Lesley Sorensen, Karthik Elumalai, Dimantha Rajapaksa, Cheng Sun +4 more 2023-03-07 $32,704,000
11396237 Battery assembly stabilization mechanism Kyle Hickey, Nicholas Dickson 2022-07-26
7723833 Stacked die packages Hien Boon Tan, Susanto Tanary, Mary Annie Cheong, Anthony Yi Sheng Sun, Chuen Khiang Wang 2010-05-25
6631093 Low power precharge scheme for memory bit lines Sudarshan Kumar, Jiann-Cherng Lan, Wenjie Jiang, Sadhana Madhyastha 2003-10-07 $52,834,000
6629194 Method and apparatus for low power memory bit line precharge Sudarshan Kumar, Sadhana Madhyastha, Jiann-Cherng Lan 2003-09-30 $25,999,000
6628539 Multi-entry register cell Sudarshan Kumar, Sadhana Madhyastha, Jiann-Cherng Lan 2003-09-30 $25,999,000
6593776 Method and apparatus for low power domino decoding Sudarshan Kumar, Vivek Joshi 2003-07-15 $37,859,000
6341099 Reducing power consumption in a data storage device Sudarshan Kumar, Sadhana Madhyastha, Jiann-Cherng Lan 2002-01-22 $877,357,000
6005417 Method and apparatus for reducing power consumption in a domino logic by reducing unnecessary toggles Yahya S. Sotoudeh, Chris L. Simone, Tsai-Chu Cheng, Chi-Kai Sin 1999-12-21 $283,710,000
5880608 Pulsed domino latches David L. Harris, S. Deo Singh 1999-03-09 $50,648,000
5821775 Method and apparatus to interface monotonic and non-monotonic domino logic David L. Harris, S. Deo Singh 1998-10-13 $57,272,000