| 8087024 |
Multiple multi-threaded processors having an L1 instruction cache and a shared L2 instruction cache |
Sridhar Lakshmanamurthy, Wilson Liao, Prashant R. Chandra, Jeen-Yuan Miin |
2011-12-27 |
| 7536692 |
Thread-based engine cache partitioning |
Sridhar Lakshmanamurthy, Wilson Liao, Prashant R. Chandra, Jeen-Yuan Miin |
2009-05-19 |
| 7313140 |
Method and apparatus to assemble data segments into full packets for efficient packet-based classification |
Sridhar Lakshmanamurthy, Charles E. Narad, Lawrence B. Huston, III, Raymond Ng, Debra Bernstein +1 more |
2007-12-25 |
| 7251219 |
Method and apparatus to communicate flow control information in a duplex network processor system |
Sridhar Lakshmanamurthy, Lawrence B. Huston, III, Raymond Ng, Hugh Wilkinson, Mark Rosenbluth +1 more |
2007-07-31 |
| 7103821 |
Method and apparatus for improving network router line rate performance by an improved system for error checking |
Sridhar Lakshmanamurthy, Charles E. Narad, Lawrence B. Huston, III, Kin-Yip Liu |
2006-09-05 |
| 7039054 |
Method and apparatus for header splitting/splicing and automating recovery of transmit resources on a per-transmit granularity |
Charles E. Narad, Larry Huston, Raymond Ng |
2006-05-02 |
| 5343086 |
Automatic voltage detector control circuitry |
Wing-Cho Fung, Eric B. Selvin |
1994-08-30 |