Issued Patents All Time
Showing 1–16 of 16 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12333309 | Differential pipeline delays in a coprocessor | Jay Fleischman, Michael Estlick, Michael Sedmak, Sneha V. Desai | 2025-06-17 |
| 12229563 | Split register list for renaming | Sree Harsha Kosuru, Eric Dixon, Michael Estlick, Patrick Michael Lowry | 2025-02-18 |
| 12223324 | Methods and apparatus for providing mask register optimization for vector operations | Michael Estlick, Eric Dixon, Theodore Carlson | 2025-02-11 |
| 12204935 | Thread forward progress and/or quality of service | Michael Estlick, Eric Dixon | 2025-01-21 |
| 12118411 | Distributed scheduler providing execution pipe balance | Sneha V. Desai, Michael Estlick, Anilkumar Ranganagoudra | 2024-10-15 |
| 11960897 | Apparatus and methods employing a shared read post register file | Michael Estlick, Eric Dixon, Todd Baumgartner | 2024-04-16 |
| 11847463 | Masked multi-lane instruction memory fault handling using fast and slow execution paths | Kai Troester, Scott Thomas Bingham, John M. King, Michael Estlick, Robert Weidner | 2023-12-19 |
| 11709681 | Differential pipeline delays in a coprocessor | Jay Fleischman, Michael Estlick, Michael Sedmak, Sneha V. Desai | 2023-07-25 |
| 11573801 | Method and apparatus for executing vector instructions with merging behavior | Eric Dixon, Theodore Carlson, Ruchir Dalal, Michael Estlick | 2023-02-07 |
| 11567554 | Clock mesh-based power conservation in a coprocessor based on in-flight instruction characteristics | Jay Fleischman, Michael Estlick, Michael Sedmak, Sneha V. Desai | 2023-01-31 |
| 11544065 | Bit width reconfiguration using a shadow-latch configured register file | Arun A. Nair, Todd Baumgartner, Michael Estlick | 2023-01-03 |
| 11451241 | Setting values of portions of registers based on bit values | Sneha V. Desai, Michael Estlick | 2022-09-20 |
| 11281466 | Register renaming after a non-pickable scheduler queue | Arun A. Nair, Michael Estlick, Sneha V. Desai, Donglin Ji | 2022-03-22 |
| 10776123 | Faster sparse flush recovery by creating groups that are marked based on an instruction type | Michael Estlick, Sneha V. Desai | 2020-09-15 |
| 9910638 | Computer-based square root and division operations | Hanbing Liu, John Kelley, Michael Estlick, Jay Fleischman | 2018-03-06 |
| 7512723 | Queued interface devices, multi-core peripheral systems, and methods for sharing a peripheral in a multi-core system | Thomas E. Tkacik, Matthew W. Brocker, Lawrence Case | 2009-03-31 |