Issued Patents All Time
Showing 1–2 of 2 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6658506 | Method and apparatus for performing timing verification of a circuit | Nevine Nassif, James Arthur Farrell, Dale Hayward Hall | 2003-12-02 |
| 6438732 | Method and apparatus for modeling gate capacitance of symmetrically and asymmetrically sized differential cascode voltage swing logic (DCVSL) | James Arthur Farrell, Harry Ray Fair, III, Nevine Nassif | 2002-08-20 |