MO

Mark H. Oskin

AM AMD: 11 patents #1,098 of 9,279Top 15%
UW University Of Washington: 7 patents #116 of 2,234Top 6%
FN F5 Networks: 4 patents #48 of 283Top 20%
Microsoft: 1 patents #24,826 of 40,388Top 65%
Overall (All Time): #179,490 of 4,157,543Top 5%
23
Patents All Time

Issued Patents All Time

Patent #TitleCo-InventorsDate
12387121 Combining quantum states of qubits on a quantum processor Salonik Resch, Anthony Gutierrez 2025-08-12
12169758 Running instances of a quantum program concurrently on a quantum processor Salonik Resch, Anthony Gutierrez, Yasuko Eckert, Vedula Venkata Srikant Bharadwaj 2024-12-17
12079145 Distribution of data and memory timing parameters across memory modules based on memory access patterns Max RUTTENBERG, Vendula Venkata Srikant Bharadwaj, Yasuko Eckert, Anthony Gutierrez 2024-09-03
11989591 Dynamically configurable overprovisioned microprocessor Anthony Gutierrez, Vedula Venkata Srikant Bharadwaj, Yasuko Eckert 2024-05-21
11922107 Quantum circuit mapping for multi-programmed quantum computers Anthony Gutierrez, Salonik Resch, Yasuko Eckert, Gabriel H. Loh, Vedula Venkata Srikant Bharadwaj 2024-03-05
11729407 Saliency-based video compression systems and methods Amrita Mazumdar, Luis Ceze 2023-08-15
11586563 Distribution of data and memory timing parameters across memory modules based on memory access patterns Max RUTTENBERG, Vendula Venkata Srikant Bharadwaj, Yasuko Eckert, Anthony Gutierrez 2023-02-21
11403221 Memory access response merging in a memory hierarchy Onur Kayiran, Yasuko Eckert, Gabriel H. Loh, Steven Raasch, Maxim V. Kazakov 2022-08-02
11226900 Using a bloom filter to reduce the number of memory addressees tracked by a coherence directory Weon Taek Na, Yasuko Eckert, Gabriel H. Loh, William L. Walker, Michael W. Boyer 2022-01-18
10437736 Single instruction multiple data page table walk scheduling at input output memory management unit Arkaprava Basu, Eric Van Tassell, Guilherme Cox, Gabriel H. Loh 2019-10-08
10318153 Techniques for changing management modes of multilevel memory hierarchy Sergey Blagodurov, Mitesh R. Meswani, Gabriel H. Loh, Mauricio Breternitz, Mark Richard Nutter +3 more 2019-06-11
10261916 Adaptive extension of leases for entries in a translation lookaside buffer Amro Awad, Sergey Blagodurov, Arkaprava Basu, Gabriel H. Loh, Andrew G. Kegel +2 more 2019-04-16
10078588 Using leases for entries in a translation lookaside buffer Arkaprava Basu, Gabriel H. Loh, Andrew G. Kegel, David S. Christie, Kevin J. McGrath 2018-09-18
9086969 Establishing a useful debugging state for multithreaded computer program Kaya Bekiroglu, Andrew Michalski Schwerin, Peter J. Godman 2015-07-21
9009020 Automatic identification of interesting interleavings in a multithreaded program Peter J. Godman, Andrew Michalski Schwerin, Andrew Whitaker, Lucas Michael Kreger-Stickles, Kaya Bekiroglu 2015-04-14
8745440 Computer-implemented system and method for providing software fault tolerance Luis Ceze, Peter J. Godman 2014-06-03
8739163 Critical path deterministic execution of multithreaded applications in a transactional memory system Luis Ceze, Joseph Devietti, Brandon Lucia 2014-05-27
8694997 Deterministic serialization in a transactional memory system based on thread creation order Luis Ceze 2014-04-08
8612955 Wavescalar architecture having a wave order memory Steven Swanson, Susan J. Eggers 2013-12-17
8453120 Enhanced reliability using deterministic multiprocessing-based synchronized replication Luis Ceze, Peter J. Godman 2013-05-28
7657882 Wavescalar architecture having a wave order memory Steven Swanson, Susan J. Eggers 2010-02-02
7598766 Customized silicon chips produced using dynamically configurable polymorphic network Martha Mercaldi-Kim, John D. Davis, Todd Michael Austin, Mojtaba Mehrara 2009-10-06
7490218 Building a wavecache Susan J. Eggers, Martha Mercaldi, Kenneth Michelson, Andrew Petersen, Andrew Putnam +2 more 2009-02-10