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Providing data from portions of a memory to processors in memory (PIMs) in an electronic device |
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Condensed coherence directory entries for processing-in-memory |
Travis Henry Boraten, Varun Agrawal |
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| 12332795 |
Reducing probe filter accesses for processing in memory requests |
Johnathan Alsop |
2025-06-17 |
| 12197329 |
Range-based cache flushing |
Preyesh Dalmia |
2025-01-14 |
| 11513802 |
Compressing micro-operations in scheduler entries in a processor |
John Kalamatianos, Pritam Majumder |
2022-11-29 |
| 11226900 |
Using a bloom filter to reduce the number of memory addressees tracked by a coherence directory |
Weon Taek Na, Yasuko Eckert, Mark H. Oskin, Gabriel H. Loh, William L. Walker |
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| 10838864 |
Prioritizing local and remote memory access in a non-uniform memory access architecture |
Onur Kayiran, Yasuko Eckert, Steven Raasch, Muhammad Shoaib Bin Altaf |
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| 10705958 |
Coherency directory entry allocation based on eviction costs |
Gabriel H. Loh, Yasuko Eckert, William L. Walker |
2020-07-07 |
| 10503641 |
Cache coherence for processing in memory |
Nuwan Jayasena |
2019-12-10 |
| 10310981 |
Method and apparatus for performing memory prefetching |
Yasuko Eckert, Nuwan Jayasena, Reena Panda, Onur Kayiran |
2019-06-04 |
| 10282295 |
Reducing cache footprint in cache coherence directory |
William L. Walker, Yasuko Eckert, Gabriel H. Loh |
2019-05-07 |
| 10049044 |
Asynchronous cache flushing |
Gabriel H. Loh, Nuwan Jayasena |
2018-08-14 |
| 10042762 |
Light-weight cache coherence for data processors with limited data sharing |
Nuwan Jayasena |
2018-08-07 |
| 7207075 |
Interchangeable gooseneck faucet |
Graham Peterson |
2007-04-24 |
| D517657 |
Faucet housing |
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2006-03-21 |