Issued Patents All Time
Showing 1–15 of 15 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12387766 | Providing data from portions of a memory to processors in memory (PIMs) in an electronic device | Alexandru Dutu, Vaibhav Ramakrishnan Ramachandran | 2025-08-12 |
| 12380029 | Condensed coherence directory entries for processing-in-memory | Travis Henry Boraten, Varun Agrawal | 2025-08-05 |
| 12332795 | Reducing probe filter accesses for processing in memory requests | Johnathan Alsop | 2025-06-17 |
| 12197329 | Range-based cache flushing | Preyesh Dalmia | 2025-01-14 |
| 11513802 | Compressing micro-operations in scheduler entries in a processor | John Kalamatianos, Pritam Majumder | 2022-11-29 |
| 11226900 | Using a bloom filter to reduce the number of memory addressees tracked by a coherence directory | Weon Taek Na, Yasuko Eckert, Mark H. Oskin, Gabriel H. Loh, William L. Walker | 2022-01-18 |
| 10838864 | Prioritizing local and remote memory access in a non-uniform memory access architecture | Onur Kayiran, Yasuko Eckert, Steven Raasch, Muhammad Shoaib Bin Altaf | 2020-11-17 |
| 10705958 | Coherency directory entry allocation based on eviction costs | Gabriel H. Loh, Yasuko Eckert, William L. Walker | 2020-07-07 |
| 10503641 | Cache coherence for processing in memory | Nuwan Jayasena | 2019-12-10 |
| 10310981 | Method and apparatus for performing memory prefetching | Yasuko Eckert, Nuwan Jayasena, Reena Panda, Onur Kayiran | 2019-06-04 |
| 10282295 | Reducing cache footprint in cache coherence directory | William L. Walker, Yasuko Eckert, Gabriel H. Loh | 2019-05-07 |
| 10049044 | Asynchronous cache flushing | Gabriel H. Loh, Nuwan Jayasena | 2018-08-14 |
| 10042762 | Light-weight cache coherence for data processors with limited data sharing | Nuwan Jayasena | 2018-08-07 |
| 7207075 | Interchangeable gooseneck faucet | Graham Peterson | 2007-04-24 |
| D517657 | Faucet housing | John Crowell, Andrew Vellrath, Graham H. Paterson | 2006-03-21 |