Issued Patents All Time
Showing 76–100 of 117 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9377954 | System and method for memory allocation in a multiclass memory system | Mitesh R. Meswani, Michael Ignatowski, Mark Richard Nutter | 2016-06-28 |
| 9367466 | Conditional prefetching | Matthew R. Poremba | 2016-06-14 |
| 9361956 | Performing logical operations in a memory | Hye Ran Jeon | 2016-06-07 |
| 9344091 | Die-stacked memory device with reconfigurable logic | Nuwan Jayasena, Michael Schulte, Michael Ignatowski | 2016-05-17 |
| 9331053 | Stacked semiconductor chip device with phase change material | Manish Arora, Nuwan Jayasena, Michael Schulte | 2016-05-03 |
| 9286948 | Query operations for stacked-die memory device | Nuwan Jayasena, James M. O'Connor, Yasuko Eckert | 2016-03-15 |
| 9251081 | Management of caches | Kai K. Chang, Yasuko Eckert, Lisa R. Hsu | 2016-02-02 |
| 9251069 | Mechanisms to bound the presence of cache blocks with specific properties in caches | Yasuko Eckert, Mauricio Breternitz, James M. O'Connor, Srilatha Manne, Nuwan Jayasena +1 more | 2016-02-02 |
| 9244629 | Method and system for asymmetrical processing with managed data affinity | Lisa R. Hsu, James M. O'Connor, Nuwan Jayasena | 2016-01-26 |
| 9235528 | Write endurance management techniques in the logic layer of a stacked memory | Lisa R. Hsu, Michael Ignatowski, Michael Schulte, Nuwan Jayasena, James M. O'Connor | 2016-01-12 |
| 9235514 | Predicting outcomes for memory requests in a cache memory | Jaewoong Sim | 2016-01-12 |
| 9229803 | Dirty cacheline duplication | Vilas Sridharan, James M. O'Connor, Jaewoong Sim | 2016-01-05 |
| 9218204 | Processing engine for complex atomic operations | James M. O'Connor, Michael Schulte, Nuwan Jayasena | 2015-12-22 |
| 9201777 | Quality of service support using stacked memory device with logic die | Lisa R. Hsu, Bradford M. Beckmann, Michael Ignatowski | 2015-12-01 |
| 9183055 | Selecting a resource from a set of resources for performing an operation | Bradford M. Beckmann, Mithuna S. Thottethodi, James M. O'Connor, Mauricio Breternitz, Lisa R. Hsu +1 more | 2015-11-10 |
| 9170948 | Cache coherency using die-stacked memory device with logic die | Bradford M. Beckmann, Lisa R. Hsu, Michael Ignatowski, Michael Schulte | 2015-10-27 |
| 9146846 | Programmable physical address mapping for memory | Mauricio Breternitz | 2015-09-29 |
| 9135185 | Die-stacked memory device providing data translation | Bradford M. Beckmann, James M. O'Connor, Michael Ignatowski, Michael Schulte, Lisa R. Hsu +1 more | 2015-09-15 |
| 9106260 | Parity data management for a memory architecture | James M. O'Connor, Vilas Sridharan | 2015-08-11 |
| 9098417 | Partitioning caches for sub-entities in computing devices | Jaewoong Sim | 2015-08-04 |
| 9087561 | Hybrid cache | Matthew R. Poremba | 2015-07-21 |
| 9075730 | Mechanisms to bound the presence of cache blocks with specific properties in caches | Mithuna S. Thottethodi, James M. O'Connor, Yasuko Eckert, Bradford M. Beckmann | 2015-07-07 |
| 9065722 | Die-stacked device with partitioned multi-hop network | Mithuna S. Thottethodi | 2015-06-23 |
| 9053039 | Installation cache | Matthew R. Poremba | 2015-06-09 |
| 9026731 | Memory scheduling for RAM caches based on tag caching | Jaewoong Sim | 2015-05-05 |