Issued Patents All Time
Showing 26–50 of 117 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11226900 | Using a bloom filter to reduce the number of memory addressees tracked by a coherence directory | Weon Taek Na, Yasuko Eckert, Mark H. Oskin, William L. Walker, Michael W. Boyer | 2022-01-18 |
| 11132300 | Memory hierarchy using page-based compression | James M. O'Connor | 2021-09-28 |
| 11106600 | Cache replacement based on translation lookaside buffer evictions | Paul James Moyer | 2021-08-31 |
| 11018125 | Multi-chip package with offset 3D structure | Milind S. Bhagavat, Rahul Agarwal | 2021-05-25 |
| 10740029 | Expandable buffer for memory transactions | William L. Walker | 2020-08-11 |
| 10714462 | Multi-chip package with offset 3D structure | Milind S. Bhagavat, Rahul Agarwal | 2020-07-14 |
| 10705958 | Coherency directory entry allocation based on eviction costs | Michael W. Boyer, Yasuko Eckert, William L. Walker | 2020-07-07 |
| 10671722 | Mechanism for throttling untrusted interconnect agents | Maurice B. Steinman | 2020-06-02 |
| 10628124 | Stochastic rounding logic | — | 2020-04-21 |
| 10540290 | Method and apparatus for translation lookaside buffer with multiple compressed encodings | Jimshed Mirza | 2020-01-21 |
| 10522193 | Processor with host and slave operating modes stacked with memory | Nuwan Jayasena, Bradford M. Beckmann, James M. O'Connor, Lisa R. Hsu | 2019-12-31 |
| 10437736 | Single instruction multiple data page table walk scheduling at input output memory management unit | Arkaprava Basu, Eric Van Tassell, Mark H. Oskin, Guilherme Cox | 2019-10-08 |
| 10394726 | Network of memory modules with logarithmic access | — | 2019-08-27 |
| 10339067 | Mechanism for reducing page migration overhead in memory systems | Yasuko Eckert, Thiruvengadam Vijayaraghavan | 2019-07-02 |
| 10318340 | NVRAM-aware data processing system | Sergey Blagodurov, Mauricio Breternitz | 2019-06-11 |
| 10318153 | Techniques for changing management modes of multilevel memory hierarchy | Sergey Blagodurov, Mitesh R. Meswani, Mauricio Breternitz, Mark Richard Nutter, John R. Slice +3 more | 2019-06-11 |
| 10303602 | Preemptive cache management policies for processing units | Onur Kayiran, Yasuko Eckert | 2019-05-28 |
| 10282295 | Reducing cache footprint in cache coherence directory | William L. Walker, Michael W. Boyer, Yasuko Eckert | 2019-05-07 |
| 10282292 | Cluster-based migration in a multi-level memory hierarchy | Andreas Prodromou, Mitesh R. Meswani, Arkaprava Basu, Nuwan Jayasena | 2019-05-07 |
| 10261916 | Adaptive extension of leases for entries in a translation lookaside buffer | Amro Awad, Sergey Blagodurov, Arkaprava Basu, Mark H. Oskin, Andrew G. Kegel +2 more | 2019-04-16 |
| 10255190 | Hybrid cache | — | 2019-04-09 |
| 10235290 | Hot page selection in multi-level memory hierarchies | Sergey Blagodurov, Mitesh R. Meswani | 2019-03-19 |
| 10158712 | Source-side resource request network admission control | Eric Christopher Morton | 2018-12-18 |
| 10133678 | Method and apparatus for memory management | Yasuko Eckert, Syed Ali Jafri, Srilatha Manne | 2018-11-20 |
| 10079044 | Processor with host and slave operating modes stacked with memory | Nuwan Jayasena, Bradford M. Beckmann, James M. O'Connor, Lisa R. Hsu | 2018-09-18 |