Issued Patents All Time
Showing 1–23 of 23 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9575891 | Sidecar SRAM for high granularity in floor plan aspect ratio | John R. Riley, Russell Schreiber, John Wuu, William McGee | 2017-02-21 |
| 9159409 | Method and apparatus for providing complimentary state retention | John Wuu | 2015-10-13 |
| 8695886 | Memory chip device | — | 2014-04-15 |
| 8276039 | Error detection device and methods thereof | John Wuu, Samuel D. Naffziger | 2012-09-25 |
| 8076236 | SRAM bit cell with self-aligned bidirectional local interconnects | Richard T. Schultz | 2011-12-13 |
| 7724578 | Sensing device for floating body cell memory and method thereof | Michael A. Dreesen, John Wuu | 2010-05-25 |
| 7430145 | System and method for avoiding attempts to access a defective portion of memory | John Wuu, Charles Morrganti | 2008-09-30 |
| 7133319 | Programmable weak write test mode (PWWTM) bias generation having logic high output default mode | John Wuu, Blaine Stackhouse | 2006-11-07 |
| 7076376 | System and method for calibrating weak write test mode (WWTM) | Richard L. Woodruff, John Wuu | 2006-07-11 |
| 6550034 | Built-in self test for content addressable memory | Reid James Riedlinger | 2003-04-15 |
| 6493855 | Flexible cache architecture using modular arrays | Samuel D. Naffziger | 2002-12-10 |
| 6366526 | Static random access memory (SRAM) array central global decoder system and method | Samuel D. Naffziger, John Wuu | 2002-04-02 |
| 6363006 | Asymmetric RAM cell | Samuel D. Naffziger | 2002-03-26 |
| 6292093 | Multi-bit comparator | Shyang Su | 2001-09-18 |
| 6285579 | System and method for enabling/disabling SRAM banks for memory access | Reid James Riedlinger | 2001-09-04 |
| 6249465 | Redundancy programming using addressable scan paths to reduce the number of required fuses | Jay Fleischman, Jeffery C Brauch | 2001-06-19 |
| 6243287 | Distributed decode system and method for improving static random access memory (SRAM) density | Samuel D. Naffziger, John Wuu | 2001-06-05 |
| 6240009 | Asymmetric ram cell | Samuel D. Naffziger | 2001-05-29 |
| 6226217 | Register structure with a dual-ended write mechanism | Reid James Riedlinger | 2001-05-01 |
| 6208565 | Multi-ported register structure utilizing a pulse write mechanism | Reid James Riedlinger | 2001-03-27 |
| 6192001 | Integrated weak write test mode (WWWTM) | John Wuu, Reid James Riedlinger | 2001-02-20 |
| 5986923 | Method and apparatus for improving read/write stability of a single-port SRAM cell | Kevin X. Zhang | 1999-11-16 |
| 5787041 | System and method for improving a random access memory (RAM) | J. Michael Hill | 1998-07-28 |