Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
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Richard T. Schultz — 78 Patents

AMD: 41 patents #203 of 9,280Top 3%
LSLsi: 34 patents #42 of 3,238Top 2%
Globalfoundries: 4 patents #817 of 4,424Top 20%
Fort Collins, CO: #13 of 3,421 inventorsTop 1%
Colorado: #149 of 40,980 inventorsTop 1%
Overall (All Time): #23,712 of 4,157,543Top 1%
78 Patents All Time
Richard T. Schultz has been granted 78 US patents while listed as an inventor at AMD. The first was granted in 1999 and the most recent in December 2025. Richard T. Schultz ranks #23,712 of 4,157,543 US inventors in our database (top 0.57%). Patent records list Richard T. Schultz in Fort Collins, CO, US.

Issued Patents All Time

Showing 1–25 of 78 patents

Patent #TitleCo-InventorsDateApprox Value ⓘ
12513943 Apparatuses and systems for offset cross field-effect transistors 2025-12-30
12455999 Metal zero power ground stub route to reduce cell area and improve cell placement at the chip level 2025-10-28
12308370 Cross field effect transistors (XFETs) in integrated circuits 2025-05-20
12274046 Cross FET SRAM cell layout 2025-04-08
12205897 Standard cell design architecture for reduced voltage droop utilizing reduced contacted gate poly pitch and dual height cells 2025-01-21
11934764 Routing and manufacturing with a minimum area metal structure Wenyi Yin, Tanmoy Saha 2024-03-19 $317,160,000
11881393 Cross field effect transistor library cell architecture design 2024-01-23 $234,019,000
11862640 Cross field effect transistor (XFET) library architecture power routing 2024-01-02 $275,976,000
11778803 Cross FET SRAM cell layout 2023-10-03 $285,241,000
11742289 Semiconductor chip with stacked conductor lines and air gaps 2023-08-29 $158,005,000
11710698 Dual-track bitline scheme for 6T SRAM cells John Wuu 2023-07-25 $204,977,000
11652050 Inset power post and strap architecture with reduced voltage droop 2023-05-16 $437,458,000
11437316 Folded cell layout for 6T SRAM cell John Wuu 2022-09-06 $151,168,000
11424336 Gate contact over active region in cell 2022-08-23 $399,915,000
11347925 Power grid architecture and optimization with EUV lithography 2022-05-31 $369,633,000
11211330 Standard cell layout architectures and drawing styles for 5nm and beyond 2021-12-28 $188,037,000
11189569 Power grid layout designs for integrated circuits Regina Tien Schmidt, Derek Peterson, Te-Hsuan Chen, Elizabeth C. Conrad, Catherina Simona Matheis Ionescu +1 more 2021-11-30 $383,963,000
11120190 Metal zero power ground stub route to reduce cell area and improve cell placement at the chip level 2021-09-14 $133,254,000
11004791 Semiconductor chip with stacked conductor lines and air gaps 2021-05-11 $234,964,000
10818762 Gate contact over active region in cell 2020-10-27 $44,640,000
10796061 Standard cell and power grid architectures with EUV lithography 2020-10-06 $81,398,000
10784154 Double spacer immersion lithography triple patterning flow and method 2020-09-22 $76,515,000
10756164 Sinusoidal shaped capacitor architecture in oxide 2020-08-25 $129,699,000
10651164 Metal zero contact via redundancy on output nodes and inset power rail architecture 2020-05-12 $51,452,000
10608076 Oscillating capacitor architecture in polysilicon for improved capacitance 2020-03-31 $59,042,000