Issued Patents All Time
Showing 25 most recent of 76 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12308370 | Cross field effect transistors (XFETs) in integrated circuits | — | 2025-05-20 |
| 12274046 | Cross FET SRAM cell layout | — | 2025-04-08 |
| 12205897 | Standard cell design architecture for reduced voltage droop utilizing reduced contacted gate poly pitch and dual height cells | — | 2025-01-21 |
| 11934764 | Routing and manufacturing with a minimum area metal structure | Wenyi Yin, Tanmoy Saha | 2024-03-19 |
| 11881393 | Cross field effect transistor library cell architecture design | — | 2024-01-23 |
| 11862640 | Cross field effect transistor (XFET) library architecture power routing | — | 2024-01-02 |
| 11778803 | Cross FET SRAM cell layout | — | 2023-10-03 |
| 11742289 | Semiconductor chip with stacked conductor lines and air gaps | — | 2023-08-29 |
| 11710698 | Dual-track bitline scheme for 6T SRAM cells | John Wuu | 2023-07-25 |
| 11652050 | Inset power post and strap architecture with reduced voltage droop | — | 2023-05-16 |
| 11437316 | Folded cell layout for 6T SRAM cell | John Wuu | 2022-09-06 |
| 11424336 | Gate contact over active region in cell | — | 2022-08-23 |
| 11347925 | Power grid architecture and optimization with EUV lithography | — | 2022-05-31 |
| 11211330 | Standard cell layout architectures and drawing styles for 5nm and beyond | — | 2021-12-28 |
| 11189569 | Power grid layout designs for integrated circuits | Regina Tien Schmidt, Derek Peterson, Te-Hsuan Chen, Elizabeth C. Conrad, Catherina Simona Matheis Ionescu +1 more | 2021-11-30 |
| 11120190 | Metal zero power ground stub route to reduce cell area and improve cell placement at the chip level | — | 2021-09-14 |
| 11004791 | Semiconductor chip with stacked conductor lines and air gaps | — | 2021-05-11 |
| 10818762 | Gate contact over active region in cell | — | 2020-10-27 |
| 10796061 | Standard cell and power grid architectures with EUV lithography | — | 2020-10-06 |
| 10784154 | Double spacer immersion lithography triple patterning flow and method | — | 2020-09-22 |
| 10756164 | Sinusoidal shaped capacitor architecture in oxide | — | 2020-08-25 |
| 10651164 | Metal zero contact via redundancy on output nodes and inset power rail architecture | — | 2020-05-12 |
| 10608076 | Oscillating capacitor architecture in polysilicon for improved capacitance | — | 2020-03-31 |
| 10438937 | Metal zero contact via redundancy on output nodes and inset power rail architecture | — | 2019-10-08 |
| 10304728 | Double spacer immersion lithography triple patterning flow and method | — | 2019-05-28 |