Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Standard cell layout architectures and drawing styles for 5nm and beyond

Standard cell layout architectures and drawing styles for 5nm and beyond

US Patent 11211330 · Granted Dec 28, 2021

Estimated economic value: $188,037,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Apparatuses and systems for offset cross field-effect transistors2025
Metal zero power ground stub route to reduce cell area and improve cell placemen2025
Cross field effect transistors (XFETs) in integrated circuits2025
Cross FET SRAM cell layout2025
Standard cell design architecture for reduced voltage droop utilizing reduced co2025
Routing and manufacturing with a minimum area metal structure2024
Cross field effect transistor library cell architecture design2024
Cross field effect transistor (XFET) library architecture power routing2024
Cross FET SRAM cell layout2023
Semiconductor chip with stacked conductor lines and air gaps2023
Dual-track bitline scheme for 6T SRAM cells2023
Inset power post and strap architecture with reduced voltage droop2023