Te-Hsuan Chen — 5 Patents at AMD

Te-Hsuan Chen has been granted 5 US patents while listed as an inventor at AMD. The first was granted in 2012 and the most recent in December 2025. Te-Hsuan Chen ranks #907,971 of 4,157,543 US inventors in our database (top 21.8%). Patent records list Te-Hsuan Chen in Tainan, MA, TW.

Issued Patents All Time

Showing 1–5 of 5 patents

Patent #	Title	Co-Inventors	Date	Approx Value ⓘ
12488171	Through silicon via macro with dense layout for placement in an integrated circuit floorplan	Michael Griffith, Aaron Keiichi Horiuchi, Donald Clay, Eric Busta, Hye Jung Stanford +5 more	2025-12-02
12339632	Training method for semiconductor process prediction model, semiconductor process prediction device, and semiconductor process prediction method	Chia-Wei Chen, Ching-Pei Lin, Chung-Yi Chiu, Ming-Wei Chen, Hsiao-Ying Yang	2025-06-24
11609836	Operation method and operation device of failure detection and classification model	Ching-Pei Lin, Ji-Fu Kung, Yi-Lin HUNG	2023-03-21	$1,904,000
11189569	Power grid layout designs for integrated circuits	Richard T. Schultz, Regina Tien Schmidt, Derek Peterson, Elizabeth C. Conrad, Catherina Simona Matheis Ionescu +1 more	2021-11-30	$383,963,000
8307261	Non-volatile memory management method	Cheng-Wen Wu, Yu Ying Hsiao, Yu-Tsao Hsing	2012-11-06

Te-Hsuan Chen — 5 Patents

Issued Patents All Time

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