Issued Patents All Time
Showing 51–75 of 76 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7308627 | Self-timed reliability and yield vehicle with gated data and clock | Derryl D. J. Allman, Jan Fure | 2007-12-11 |
| 7284213 | Defect analysis using a yield vehicle | Jan Fure, Derryl D. J. Allman | 2007-10-16 |
| 7183791 | Reliability circuit for applying an AC stress signal or DC measurement to a transistor device | John D. Walker, SangJune Park | 2007-02-27 |
| 7181713 | Static timing and risk analysis tool | — | 2007-02-20 |
| 7154734 | Fully shielded capacitor cell structure | Jeffrey P. Burleson, Steven L. Howard | 2006-12-26 |
| 7129101 | Failure analysis vehicle for yield enhancement with self test at speed burnin capability for reliability testing | Michael Schmidt | 2006-10-31 |
| 7023252 | Chip level clock tree deskew circuit | — | 2006-04-04 |
| 7016794 | Floor plan development electromigration and voltage drop analysis tool | — | 2006-03-21 |
| 6861864 | Self-timed reliability and yield vehicle array | — | 2005-03-01 |
| 6851098 | Static timing analysis and performance diagnostic display tool | — | 2005-02-01 |
| 6830984 | Thick traces from multiple damascene layers | Peter J. Wright | 2004-12-14 |
| 6781151 | Failure analysis vehicle | Steve Howard | 2004-08-24 |
| 6675139 | Floor plan-based power bus analysis and design tool for integrated circuits | Mark W. Jetton, Richard A. Laubhan | 2004-01-06 |
| 6671846 | Method of automatically generating schematic and waveform diagrams for isolating faults from multiple failing paths in a circuit using input signal predictors and transition times | — | 2003-12-30 |
| 6653883 | Process, voltage and temperature independent clock tree deskew circuitry-temporary driver method | — | 2003-11-25 |
| 6653726 | Power redistribution bus for a wire bonded integrated circuit | Roger D. Weir | 2003-11-25 |
| 6625770 | Method of automatically generating schematic and waveform diagrams for relevant logic cells of a circuit using input signal predictors and transition times | — | 2003-09-23 |
| 6442741 | Method of automatically generating schematic and waveform diagrams for analysis of timing margins and signal skews of relevant logic cells using input signal predictors and transition times | — | 2002-08-27 |
| 6433598 | Process, voltage and temperature independent clock tree deskew circuitry-active drive method | — | 2002-08-13 |
| 6429714 | Process, voltage and temperature independent clock tree deskew circuitry-temporary driver method | — | 2002-08-06 |
| 6408265 | Metastability risk simulation analysis tool and method | Kevin Gearhardt | 2002-06-18 |
| 6388486 | Load sensing, slew rate shaping, output signal pad cell driver circuit and method | — | 2002-05-14 |
| 6346721 | Integrated circuit having radially varying power bus grid architecture | — | 2002-02-12 |
| 6340905 | Dynamically minimizing clock tree skew in an integrated circuit | — | 2002-01-22 |
| 6111310 | Radially-increasing core power bus grid architecture | — | 2000-08-29 |