Issued Patents All Time
Showing 1–4 of 4 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8799839 | Extraction tool and method for determining maximum and minimum stage delays associated with integrated circuit interconnects | Alexander Tetelbaum | 2014-08-05 |
| 6675139 | Floor plan-based power bus analysis and design tool for integrated circuits | Mark W. Jetton, Richard T. Schultz | 2004-01-06 |
| 6182269 | Method and device for fast and accurate parasitic extraction | — | 2001-01-30 |
| 5274568 | Method of estimating logic cell delay time | Richard Blinne, Richard J. Holzer, Jr., Timothy Ouellette, Rhea R. Ozman, John Buddy Scott | 1993-12-28 |