RB

Richard Blinne

Lsi Logic: 7 patents #248 of 1,957Top 15%
LS Lsi: 4 patents #338 of 1,740Top 20%
AT AT&T: 1 patents #10,626 of 18,772Top 60%
HA Hyundai Electronics America: 1 patents #75 of 148Top 55%
Ncr: 1 patents #1,404 of 2,952Top 50%
SL Symbios Logic: 1 patents #28 of 87Top 35%
📍 Fort Collins, CO: #354 of 3,421 inventorsTop 15%
🗺 Colorado: #3,430 of 40,980 inventorsTop 9%
Overall (All Time): #387,159 of 4,157,543Top 10%
13
Patents All Time

Issued Patents All Time

Showing 1–13 of 13 patents

Patent #TitleCo-InventorsDate
7853901 Unified layer stack architecture Viswanathan Lakshmanan, Thomas R. O'Brien 2010-12-14
7302654 Method of automating place and route corrections for an integrated circuit design from physical design validation Viswanathan Lakshmanan, Michael Josephides 2007-11-27
7260803 Incremental dummy metal insertions Viswanathan Lakshmanan, Vikram Shrowty, Lena Montecillo 2007-08-21
7231626 Method of implementing an engineering change order in an integrated circuit design by windows Jason Hoff, Viswanathan Lakshmanan, Michael Josephides, Daniel W. Prevedel, Johathan P. Kuppinger 2007-06-12
7219317 Method and computer program for verifying an incremental change to an integrated circuit design Viswanathan Lakshmanan, Jonathan P. Kuppinger 2007-05-15
7111269 Comparison of two hierarchical netlist to generate change orders for updating an integrated circuit layout Lalita M. Satapathy, Santhanakris Raman 2006-09-19
7107559 Method of partitioning an integrated circuit design for physical design verification Viswanathan Lakshmanan, Jonathan P. Kuppinger 2006-09-12
7007248 Method and apparatus for implementing engineering change orders Viswanathan Lakshmanan, Venugopalan Pranesan 2006-02-28
6662349 Method of repeater insertion for hierarchical integrated circuit design David A. Morgan, James Jensen, Christopher J. Tremel 2003-12-09
6141631 Pulse rejection circuit model program and technique in VHDL Sudhir Patel 2000-10-31
5995730 Method for generating format-independent electronic circuit representations 1999-11-30
5521834 Method and apparatus for calculating dynamic power dissipation in CMOS integrated circuits Harold S. Crafts 1996-05-28
5274568 Method of estimating logic cell delay time Richard J. Holzer, Jr., Timothy Ouellette, Rhea R. Ozman, Richard A. Laubhan, John Buddy Scott 1993-12-28